pulse_synchronizer(异步信号处理)程序理解

本地地址：E:/FPGA/NetFPGA/project_top/src_for_graduate/big_fpga/gemac_group/pulse_synchronizer.v

///
// $Id: pulse_synchronizer.v 1887 2007-06-19 21:33:32Z grg $
//
// Module: pulse_synchronizer.v
// Project: UNET-SWITCH4-64bit-wbs
// Description: transforms a pulse（脉冲） from one domain（领域，范围，范畴 ） into a pulse in another domain
//              note that the arriving pulses should be separated by around 5 cycles
//              in each domain.
//
///
`timescale 1ns/1ps
  module pulse_synchronizer
    ( input pulse_in_clkA,                            //输入脉冲A
      input clkA,                                     //输入时钟A
      output pulse_out_clkB,                          //输出脉冲
      input clkB,                                     //输入时钟B
      input reset_clkA,                               //输入时钟A复位信号
      input reset_clkB                                //输入时钟B复位信号
      );

   reg      ackA;                                     //
   reg      ackB;                                     //

   reg      ackA_synch;
   reg      ackA_clkB;
   reg      ackB_synch;
   reg      ackB_clkA;

   reg      pulse_in_clkA_d1;
   reg      ackA_clkB_d1;
   reg      ackB_d1;

   /* detect rising edges in clkA domain, set the ackA signal
    * until the pulse is acked from the other domain */
   always @(posedge clkA) begin
      if(reset_clkA) begin
         ackA <&