s3c2440裸机中 option.inc C语言解释

源代码

;===========================================

; NAME: OPTION.A
; DESC: Configuration options for .S files
;===========================================


;Start address of each stacks,
_STACK_BASEADDRESS EQU 0x33ff8000  
_MMUTT_STARTADDRESS EQU 0x33ff8000
_ISR_STARTADDRESS EQU 0x33ffff00


GBLL PLL_ON_START
PLL_ON_START SETL {TRUE}




GBLL ENDIAN_CHANGE
ENDIAN_CHANGE SETL {FALSE}


GBLA ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH SETA 16




;BUSWIDTH = 16,32
GBLA    BUSWIDTH ;max. bus width for the GPIO configuration
BUSWIDTH SETA    32


GBLA UCLK
UCLK SETA 48000000


GBLA XTAL_SEL
GBLA FCLK
GBLA CPU_SEL


;(1) Select CPU
CPU_SEL SETA 32440001 ; 32440001:2440A


;(2) Select XTaL
XTAL_SEL SETA 12000000 ;Fin = 12.0MHz
;XTAL_SEL SETA 16934400


;(3) Select FCLK
;FCLK SETA 304000000
;FCLK SETA 296352000
;FCLK SETA 271500000
;FCLK SETA 100000000
;FCLK SETA 200000000
FCLK SETA 400000000




;(4) Select Clock Division (Fclk:Hclk:Pclk)
;FCLK = 100000000
;CLKDIV_VAL EQU 1 ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
;FCLK = 200000000
;CLKDIV_VAL EQU 3 ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
;FCLK = 400000000
CLKDIV_VAL EQU 5 ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
;FCLK = 304000000 or 271500000
;CLKDIV_VAL EQU 7 ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.


 [ XTAL_SEL = 12000000
 
[ FCLK = 271500000
M_MDIV EQU 173 ;Fin=12.0MHz Fout=271.5MHz
M_PDIV EQU 2
[ CPU_SEL = 32440001
M_SDIV EQU 2 ; 2440A
    |
M_SDIV EQU 1 ; 2440X
    ]
]

[ FCLK = 304000000
M_MDIV EQU 68 ;Fin=12.0MHz Fout=304.8MHz
M_PDIV EQU 1
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]


[ FCLK = 100000000
M_MDIV EQU 42 ;Fin=12.0MHz Fout=100MHz
M_PDIV EQU 4
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]


[ FCLK = 200000000
M_MDIV EQU 92 ;Fin=12.0MHz Fout=200MHz
M_PDIV EQU 4
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]


[ FCLK = 400000000
M_MDIV EQU 92 ;Fin=12.0MHz Fout=400MHz
M_PDIV EQU 1
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]

[ UCLK = 48000000
U_MDIV EQU 56 ;Fin=12.0MHz Fout=48MHz
U_PDIV EQU 2
[ CPU_SEL = 32440001
U_SDIV EQU 2 ; 2440A
    |
U_SDIV EQU 1 ; 2440X
    ]
]
[ UCLK = 96000000
U_MDIV EQU 56 ;Fin=12.0MHz Fout=96MHz
U_PDIV EQU 2
[ CPU_SEL = 32440001
U_SDIV EQU 1 ; 2440A
    |
U_SDIV EQU 0 ; 2440X
    ]


]


  | ; else if XTAL_SEL = 16.9344Mhz


[ FCLK = 266716800
M_MDIV EQU 118 ;Fin=16.9344MHz
M_PDIV EQU 2
[ CPU_SEL = 32440001
M_SDIV EQU 2 ; 2440A
|
M_SDIV EQU 1 ; 2440X
]
]

[ FCLK = 296352000
M_MDIV EQU 97 ;Fin=16.9344MHz
M_PDIV EQU 1
[ CPU_SEL = 32440001
M_SDIV EQU 2 ; 2440A
|
M_SDIV EQU 1 ; 2440X
]
]
[ FCLK = 541900800
M_MDIV EQU 120 ;Fin=16.9344MHz
M_PDIV EQU 2
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]

[ UCLK = 48000000
U_MDIV EQU 60 ;Fin=16.9344MHz Fout=48MHz
U_PDIV EQU 4
[ CPU_SEL = 32440001
U_SDIV EQU 2 ; 2440A
    |
U_SDIV EQU 1 ; 2440X
    ]
    ]
[ UCLK = 96000000
U_MDIV EQU 60 ;Fin=16.9344MHz Fout=96MHz
U_PDIV EQU 4
[ CPU_SEL = 32440001
U_SDIV EQU 1 ; 2440A
    |
U_SDIV EQU 0 ; 2440X
    ]
]

   ] ; end of if XTAL_SEL = 12000000.
  

END

C语言解释后

#define _STACK_BASEADDRESS    0x33ff8000
#define _MMUTT_STARTADDRESS   0x33ff8000
#define _ISR_STARTADDRESS     0x33ffff00   
#define CLKDIV_VAL          5
bool PLL_ON_START=false;
bool ENDIAN_CHANGE=false;


int ENTRY_BUS_WIDTH=16;
int BUSWIDTH       =32;
int UCLK           =48000000;


int XTAL_SEL   =12000000;
int FCLK =400000000 ;
int CPU_SEL=32440001;




int M_MDIV;
int M_PDIV;
int M_SDIV;


if(XTAL_SEL==12000000)
{
if(FCLK==271500000)
{
M_MDIV=173;
M_PDIV=2;
if( CPU_SEL == 32440001)
M_SDIV=2;
else
M_SDIV=1;
}
else if(FCLK==304000000)
{
M_MDIV=68;
M_PDIV=1;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
else if(FCLK==100000000)
{
M_MDIV=42;
M_PDIV=4;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
else if(FCLK==200000000)
{
M_MDIV=92;
M_PDIV=4;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
else if(FCLK==400000000)
{
M_MDIV=92;
M_PDIV=1;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
else if(FCLK==48000000)
{
M_MDIV=92;
M_PDIV=1;
if( CPU_SEL == 32440001)
M_SDIV=2;
else
M_SDIV=1;
}
else if(FCLK==96000000)
{
M_MDIV=56;
M_PDIV=2;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
}else
{
if(FCLK == 266716800)
{
M_MDIV=118;
M_PDIV=2;
if( CPU_SEL == 32440001)
M_SDIV=2;
else
M_SDIV=1;
}
else if(FCLK == 296352000)
{
M_MDIV=97;
M_PDIV=1;
if( CPU_SEL == 32440001)
M_SDIV=2;
else
M_SDIV=1;
}
else if(FCLK == 541900800)
{
M_MDIV=120;
M_PDIV=2;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}
else if(FCLK == 48000000)
{
M_MDIV=60;
M_PDIV=4;
if( CPU_SEL == 32440001)
M_SDIV=2;
else
M_SDIV=1;
}
else if(FCLK == 96000000)
{
M_MDIV=60;
M_PDIV=4;
if( CPU_SEL == 32440001)
M_SDIV=1;
else
M_SDIV=0;
}

}


参考  http://blog.sina.com.cn/s/blog_65b11dc10100pyia.html
如有不对，敬请指正！