`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
reg [2:0] cnt;
reg [5:0] seq;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 0;
end
else if(cnt == 6-1) begin
cnt <= 0;
end
else begin
cnt = cnt + 1;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seq <= 0;
end
else begin
seq = {data,seq[5:1]} ; //先放进去再移位
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 0;
not_match <= 0;
end
else if(cnt == 6-1) begin //所以在第6个时钟时刻,移位了5次,比较seq[4:0],即前5位,第六位是放进去的data
match <= (seq[5:0]==5'b01110 && data==0);
not_match<=!(seq[5:0]==5'b01110 && data==0);
end
else begin
match <= 0;
not_match <= 0;
end
end
endmodule