module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter idle = 0, start = 1, data1 = 2, data2 = 3, data3 = 4, data4 = 5, data5 = 6, data6 = 7, data7 = 8, data8 = 9, stop = 10, waitup = 11; // Use FSM from Fsm_serial
reg [3:0] state, next;
reg [7:0] data;
always @(*) begin
case (state)
idle : next <= in? idle : start;
start : next <= data1;
data1 : next <= data2;
data2 : next <= data3;
data3 : next <= data4;
data4 : next <= data5;
data5 : next <= data6;
data6 : next <= data7;
data7 : next <= data8;
data8 : next <= in? stop : waitup;
waitup : next <= in? idle : waitup;
stop : next <= in? idle : start;
endcase
end
always @(posedge clk) begin
if (reset)
state <= idle;
else
state <= next;
end
assign done = (state == stop);
always @(posedge clk) begin // 移位寄存器来存储八位数据
if (reset)
data <= 8'd0;
else begin
if (next == data1 | next == data2 | next == data3 | next == data4 | next ==
data5 | next == data6 | next == data7 | next == data8)
data <= {in, data[7:1]};
end
end
assign out_byte = done? data : 8'd0; // New: Datapath to latch input bits.
endmodule