module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A = 0, B = 1;
reg [1:0] state, next;
always @(*) begin
case (state)
A : next = s? B : A;
B : next = B;
endcase
end
reg w_reg1, w_reg2;
reg [1:0] cnt;
always @(posedge clk) begin
if (reset) begin
state <= A;
w_reg1 <= 0;
w_reg2 <= 0;
cnt <= 0;
end
else if (state == B) begin
state <= next;
w_reg1 <= w;
w_reg2 <= w_reg1;
if (cnt == 2'd2)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
else begin
state <= next;
w_reg1 <= 0;
w_reg2 <= 0;
cnt <= 1'b0;
end
end
always @(posedge clk) begin
if (reset)
z <= 0;
else if (state == B & cnt == 2'd2) begin
if (w & w_reg1 & ~w_reg2 | w & ~w_reg1 & w_reg2 | ~w & w_reg1 & w_reg2) //不可写作三值异或的形式,100同样满足异或后为0;
z <= 1;
else
z <= 0;
end
else
z <= 0;
end
endmodule
三bit信号检测,用到移位寄存器存储上两个W的状态,三bit计数(cnt)