systemverilog package的作用以及include和import的区别

1. SV package 作用

sv中的package与c++中的namespace类似，都是为了解决命名冲突的问题。不同package里面的内容是可以重名的。使用时加pkg_name::xxx来指定用哪个pkg_name里面的xxx。

The package declaration creates a scope that contains declarations intended to be shared among one or
more compilation units, modules, interfaces, or programs. Items within packages are generally type
definitions, tasks, and functions.Items within packages shall not have hierarchical references to identifiers
except those created within the package or made visible by import of another package.

值得注意的是，在package中定义的class内部，无法通过类似于force tb.xxx.yyy = 0的方式来访问DUT中的信号。

 

2. include和import的区别

include是编译预处理语句，是将文件中的内容插入到当前文件中。

import是package里面的全部identifiers 或者指定identifiers 对当前作用域可见。

The import declaration provides direct visibility of identifiers within packages. It allows identifiers
declared within packages to be visible within the current scope without a package name qualifier. Two
forms of the import declaration are provided: explicit import and wildcard import