The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
使用Verilog语言实现的10/100M MAC子层传输协议。是OSI中的数据链路层功能,完成与物理层数据交换。MAC是一个中间传输层,上层链接应用层,下层需要专门的PHY物理芯片实现与物理层管理。
下图是IP核整体框架图: