序列检测器 | 10010序列的检测

该电路的状态转换图如下图所示：

对应的Verilog程序为：

//****************************seqdet.v****************************************

module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output[2:0] state;
reg[2:0] state;
wire z;
parameter IDLE=3'd0,A=3'd1,B=3'd2,C=3'd3,D=3'd4,E=3'd5;

assign z = (state==D && x==0)?1:0 ; //Mealy状态机

always @(posedge clk)
begin
    if(!rst) state<=IDLE;
    else
        casex(state)
            IDLE: if(x==1) state<=A;
                  else state<=IDLE;
            A:    if(x==0) state<=B;
                  else state<=A;
            B:    if(x==0) state<=C;
                  else state<=A;
            C:    if(x==1) state<=D;
                  else state<=IDLE;
            D:    if(x==0) state<=E;
                  else state<=A;
            E:    if(x==0) state<=C;
                  else state<=A;
            default: state<=IDLE;
        endcase
end

endmodule

也可以把状态E去掉，状态D变为if(x==0) state<=B; else state<=A;

//****************************seqdet_TB.v****************************************

`timescale 1ns / 1ns

module seqdet_TB;
reg clk, rst;
reg[23:0] data;
wire[2:0] state;
wire z,x;
assign x=data[23];
always #10 clk=~clk;
always @(posedge clk)
    data={data[22:0],data[23]};
initial
    begin
        clk=0;
        rst=1;
        #2 rst=0;
        #30 rst=1;
        data = 24'b0000_1100_1010_0100_1001_0100;
        #500 $stop;
    end
seqdet m(x,z,clk,rst,state);

endmodule