ECE550 final review
1 datapath
1.1 single-cycle datapath
- ALU的output不一定是32位,如overflow
- 3个读依次(IMEM、reg[control ROM/random logic]、DMEM),3个写同时(DMEM、reg、PC)
- 没有读在写的后面
- 控制信号生成:根据opcode生成所有control signal(不同insn的opcode不同)
- ROM
- Random logic(‘non-repeating’)
- MCCF (make common case fast) principle
- CPI(cycle/insn) = 1 (low)
- clock period (short) 长
- performance
- MIPS(million insns per second) = IPC * Frequency(MHz) 越大越好 --> throughput 吞吐量
- Performance/Watt瓦特 --> today
1.2 multi-cycle datapath
- CPI(cycle/insn) 大
- clock period 短
2 pipelining
2.1 pipelined control
- PC从ALU stage开始就不存了,因为PC已经经计算并return back
2.2 dependences and hazards
- Hazard分为structural hazards和data hazards --> 还有control hazards
- Structural hazards --> Two insns trying to use same circuit at same time
- Data hazards --> 由data dependence产生,要加nop等待 --> 不发生在Dmem,发生在reg
- Control hazards --> 在branch insns结果知道前先默认不jump,fetch下一个insn --> nop