`timescale 1ns/10ps
module device(a,b,sel,y);
input a,b;
input [1:0]sel; //括号要写在前面
output y;
reg y;
always@(a or b or sel)//敏感变量列表要写全
begin
if(sel==1)
begin
y<=a^b;
end
else
begin
y<=a&b;
end
end
endmodule
module device_tb;
reg [3:0]absel;//输入使用reg
wire y;//输出使用wire
device device(.a(absel[0]),.b(absel[1]),.sel(absel[3:2]),.y(y));//a,b,sel都要是程序里面定义的
initial begin
absel<=0;
#200 $stop;
end
always #10 absel<=absel+1; //不要加@
endmodule
使用always(testbench不会变)modeule fn_sw_4(a,b,sel,y);input a,b;input [1:0]sel;output y ;reg y; //always 语句块里面赋值的变量需要是reg型always@(a or b or sel)//三个为敏感变量,组合逻辑输入begin if(sel==1) begin y<=a^b; end else begin y<=a&b; endend endmodule