UART

from:http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter


Universal asynchronous receiver/transmitter

From Wikipedia, the free encyclopedia

A Universal Asynchronous Receiver/Transmitter, abbreviated UART (play /ˈjuːɑrt/), is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such asEIA,RS-232,RS-422 orRS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such asdifferential signaling etc.) typically are handled by a special driver circuit external to the UART.

A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART, orDUART, combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are calledUSARTs (universal synchronous/asynchronous receiver/transmitter).

Contents

Transmitting and receiving serial data

The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion.[1] At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains ashift register, which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires.[citation needed]

The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert thelogic level signals of the UART to and from the external signaling levels. External signals may be of many different forms. Examples of standards for voltage signaling areRS-232,RS-422 and RS-485 from theEIA. Historically, current (incurrent loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such areoptical fiber, IrDA (infrared), and (wireless)Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone linemodems, RF modulation with data radios, and theDC-LIN forpower line communication.

Communication may be simplex (in one direction only, with no provision for the receiving device to send information back to the transmitting device),full duplex (both devices send and receive at the same time) orhalf duplex (devices take turns transmitting and receiving).

Character framing

Charactercode.png

The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in which the line is held high to show that the line and transmitter are not damaged. Each character is sent as a logic low start bit, a configurable number of data bits (usually 8, but legacy systems can use 5, 6, 7 or 9), an optional parity bit, and one or more logic high stop bits. The start bit signals the receiver that a new character is coming. The next five to eight bits, depending on the code set employed, represent the character. Following the data bits may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters.

Obviously a problem exists if a receiver detects a line that is low for more than one character time. This is called a "break." It is normal to detect breaks to disable a UART or switch to an alternative channel. Sometimes remote equipment is designed to reset or shut down when it receives a break. Premium UARTs can detect and create breaks.

Receiver

All operations of the UART hardware are controlled by a clock signal which runs at a multiple of the data rate. For example, each data bit may be as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processorinterrupt to request that the host processor transfers the received data.

The best UARTs "resynchronize" on each change of the data line that is more than a half-bit wide. In this way, they reliably receive when the transmitter is sending at a slightly different speed than the receiver. (This is the normal case, because communicating units usually have no shared timing system apart from the communication signal.) Simplistic UARTs may merely detect the falling edge of the start bit, and then read the center of each expected data bit. A simple UART can work well if the data rates are close enough that the stop bits are sampled reliably.

It is a standard feature for a UART to store the most recent character while receiving the next. This "double buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-outFIFO buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.

Transmitter

Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since full-duplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift registers for transmitted characters and received characters.

Application

Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.

Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second equals the bit rate divided by 10.

Some very low-cost home computers or embedded systems dispensed with a UART and used the CPU to sample the state of an input port or directly manipulate an output port for data transmission. While very CPU-intensive, since the CPU timing was critical, these schemes avoided the purchase of a UART chip that was costly in the 1970's. The technique was known as a bit-banging serial port.

Synchronous transmission

USART chips have both synchronous and asynchronous modes. In synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An asynchronous transmission sends no characters over the interconnection when the transmitting device has nothing to send; but a synchronous interface must send "pad" characters to maintain synchronization between the receiver and transmitter. The usual filler is the ASCII "SYN" character. This may be done automatically by the transmitting device.

History

Some early telegraph schemes used variable-length pulses (as in Morse code) and rotating clockwork mechanisms to transmit alphabetic characters. The first UART-like devices (with fixed-length pulses) were rotating mechanical switches (commutators). These sent 5-bitBaudot codes for mechanical teletypewriters, and replacedmorse code. Later, 6-bit codes became common to avoid the figures vs. character errors that could occur when Baudot's shift character was corrupted.ASCII was adopted by the U.S. so that the military services would all use the same teletypewriter codes. ASCII added upper and lower case, with enough punctuation to print most documents. This required a seven bit code. When U.S. telephone systems became digital in the 1960s, they used an8-bit data sample size to digitize voice. As a result, most data transmission and computers shifted to 8-bit character sizes to use the lowest cost data transmission system. For example,IBM built computers in the early 1960s with 8-bit characters, and an "upper half" of Latin I characters became common in many data networks that had formerly used 7-bit ASCII. The economic effect of the telephone system is large: It effectively forced character systems with more than 8-bits (e.g.Unicode) back into an 8-bit form (e.g.UTF-8), and most commercially important computers for the last forty years have used internal word sizes that are multiples of 8 bits.

Gordon Bell designed the UART for thePDP series of computers. The ASCII code to a teletypewriter made an excellent general-purpose I/O device for a small computer. To reduce costs, including wiring and back-plane costs, these computers also pioneeredflow control using XON and XOFF characters rather than hardware wires.

Western Digital made the first single-chip UART WD1402A around 1971; this was an early example of amedium scale integrated circuit. Another popular chip was a SCN2651 from the Signetics 2650 family.

An example of an early 1980s UART was the National Semiconductor 8250. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. For example, the popular National Semiconductor16550 has a 16 byteFIFO, and spawned many variants, including the16C550, 16C650, 16C750, and 16C850.

Depending on the manufacturer, different terms are used to identify devices that perform the UART functions.Intel called their8251 device a "Programmable Communication Interface".MOS Technology6551 was known under the name "Asynchronous Communications Interface Adapter" (ACIA). The term "Serial Communications Interface" (SCI) was first used atMotorola around 1975 to refer to their start-stop asynchronous serial interface device, which others were calling a UART.

Structure

A UART usually contains the following components:

  • a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period.
  • input and output shift registers
  • transmit/receive control
  • read/write control logic
  • transmit/receive buffers (optional)
  • parallel data bus buffer (optional)
  • First-in, first-out (FIFO) buffer memory (optional)

Special receiver conditions

Overrun error

An "overrun error" occurs when the receiver cannot process the character that just came in before the next one arrives. Various devices have different amounts of buffer space to hold received characters. The CPU must service the UART in order to remove characters from the input buffer. If the CPU does not service the UART quickly enough and the buffer becomes full, an Overrun Error will occur, and incoming characters will be lost.

Underrun error

An "underrun error" occurs when the UART transmitter has completed sending a character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems.

Framing error

A "framing error" occurs when the designated "start" and "stop" bits are not valid. As the "start" bit is used to identify the beginning of an incoming character, it acts as a reference for the remaining bits. If the data line is not in the expected idle state when the "stop" bit is expected, a Framing Error will occur.

Parity error

A "parity error" occurs when the number of "active" bits does not agree with the specified parity configuration of the USART, producing aParity Error. Because the "parity" bit is optional, this error will not occur if parity has been disabled. Parity error is set when the parity of an incoming data character does not match the expected value.

Break condition

A "break condition" occurs when the receiver input is at the "space" level for longer than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error.

Some equipment will deliberately transmit the "break" level for longer than a character as an out-of-band signal. When signaling rates are mismatched, no meaningful characters can be sent, but a long "break" signal can be a useful way to get the attention of a mismatched receiver to do something (such as resetting itself). Unix-like systems can use the long "break" level as a request to change the signaling rate, to support dial-in access at multiple signaling rates.

UART models

ModelDescription
EXAR XR21V1410
Intersil 6402
CDP 1854 (RCA, now Intersil)
Zilog Z84402000 kbit/s. Async, Bisync, SDLC, HDLC, X.25. CRC. 4-byte RX buffer. 2-byte TX buffer. DMA.[2]
8250Obsolete with 1-byte buffers
8251
Motorola 6850
6522
6551
Rockwell 65C52
16450
16550
16550A16-byte buffers, TL=1,4,8,14; 115.2 kbit/s standard, many support 230.4 or 460.8 kbit/s. DMA-mode.[3]
16C552
1665032-byte buffers. 460.8 kbit/s.
1675064-byte buffer for send, 56-byte for receive. 921.6 kbit/s.
16850128-byte buffers. 460.8 kbit/s or 1500 kbit/s.
16C850
16950
Hayes ESP1 kB buffers, 921.6 kbit/s, 8-ports.[4]

UART in modems

Modems for personal computers that plug into a motherboard slot must also include the UART function on the card. The original 8250 UART chip shipped with the IBM personal computer had no on-chip buffering for received characters, which meant that communications software performed poorly at speeds above 9600 bits/second, especially if operating under a multitasking system or if handling interrupts from disk controllers. High-speed modems used UARTs that were compatible with the original chip but which included additional FIFO buffers, giving software additional time to respond to incoming data.

A look at the performance requirements at high bit rates shows why the 16, 32, 64 or 128 byte FIFO is a necessity. The Microsoft specification for a DOS system requires that interrupts not be disabled for more than 1 millisecond at a time. Some hard disk drives and video controllers violate this specification. 9600 bit/s will deliver a character approximately every millisecond, so a 1 byte FIFO should be sufficient at this rate on a DOS system which meets the maximum interrupt disable timing. Rates above this may receive a new character before the old one has been fetched, and thus the old character will be lost. This is referred to as an overrun error and results in one or more lost characters. With error correcting modems, any lost characters will be retransmitted, but retransmission slows the connection.

A 16 byte FIFO allows up to 16 characters to be received before the computer has to service the interrupt. This increases the maximum bit rate the computer can process reliably from 9600 to 153,000 bit/s if it has a 1 millisecond interrupt dead time. A 32 byte FIFO increases the maximum rate to over 300,000 bit/s. A second benefit to having a FIFO is that the computer only has to service about 8 to 12% as many interrupts, allowing more CPU time for updating the screen, or doing other chores. Thus the computer's responses will improve as well.




计算机中的UART

  UART是计算机串行通信端口的关键部分。在计算机中,UART相连于产生兼容RS232规范信号的电路。RS232标准定义逻辑“1”信号相对于地为-3到-15伏,而逻辑“0”相对于地为3到15伏。所以,当一个微控制器中的UART相连于PC时,它需要一个RS232驱动器来转换电平。  Uart这里指的是TTL电平的串口;RS232指的是RS232电平的串口。  TTL电平是3.3V的,而RS232是负逻辑电平,它定义+5~+12V为低电平,而-12~-5V为高电平。  Uart串口的RXD、TXD等一般直接与处理器芯片的引脚相连,而RS232串口的RXD、TXD等一般需要经过电平转换(通常由Max232等芯片进行电平转换)才能接到处理器芯片的引脚上,否则这么高的电压很可能会把芯片烧坏。  我们平时所用的电脑的串口就是RS232的,当我们在做电路工作时,应该注意下外设的串口是Uart类型的还是RS232类型的,如果不匹配,应当找个转换线(通常这根转换线内有块类似于Max232的芯片做电平转换工作的),可不能盲目地将两串口相连

编辑本段Uart协议

  UART作为异步串口通信协议的一种,工作原理是将传输数据的每个字符一位接一位地传输。  其中各位的意义如下:  起始位:先发出一个逻辑”0”的信号,表示传输字符的开始。  资料位:紧接着起始位之后。资料位的个数可以是4、5、6、7、8等,构成一个字符。通常采用ASCII码。从最低位开始传送,靠时钟定位。  奇偶校验位:资料位加上这一位后,使得“1”的位数应为偶数(偶校验)或奇数(奇校验),以此来校验资料传送的正确性。  停止位:它是一个字符数据的结束标志。可以是1位、1.5位、2位的高电平。 由于数据是在传输线上定时的,并且每一个设备有其自己的时钟,很可能在通信中两台设备间出现了小小的不同步。因此停止位不仅仅是表示传输的结束,并且提供计算机校正时钟同步的机会。适用于停止位的位数越多,不同时钟同步的容忍程度越大,但是数据传输率同时也越慢。  空闲位:处于逻辑“1”状态,表示当前线路上没有资料传送。  波特率:是衡量资料传送速率的指针。表示每秒钟传送的二进制位数。例如资料传送速率为120字符/秒,而每一个字符为10位,则其传送的波特率为10×120=1200位/秒=1200波特。  UART的作用  1. 发送/接收逻辑  发送逻辑对从发送FIFO 读取的数据执行“并→串”转换。控制逻辑输出起始位在先的串行位流,并且根据控制寄存器中已编程的配置,会面紧跟着数据位(注意:最低位 LSB 先输出)、奇偶校验位和停止位。  在检测到一个有效的起始脉冲后,接收逻辑对接收到的位流执行“串→并”转换。此外还会对溢出错误、奇偶校验错误、帧错误和线中止(line-break)错误进行检测,并将检测到的状态附加到被写入接收FIFO 的数据中。  2. 波特率的产生  波特率除数(baud-rate divisor)是一个22 位数,它由16 位整数和6 位小数组成。波特率发生器使用这两个值组成的数字来决定位周期。通过带有小数波特率的除法器,在足够高的系统时钟速率下,UART 可以产生所有标准的波特率,而误差很小。  3. 数据收发  发送时,数据被写入发送FIFO。如果UART 被使能,则会按照预先设置好的参数(波特率、数据位、停止位、校验位等)开始发送数据,一直到发送FIFO 中没有数据。一旦向发送FIFO 写数据(如果FIFO 未空),UART 的忙标志位BUSY 就有效,并且在发送数据期间一直保持有效。BUSY 位仅在发送FIFO 为空,且已从移位寄存器发送最后一个字符,包括停止位时才变无效。即 UART 不再使能,它也可以指示忙状态。BUSY 位的相关库函数是UARTBusy( )  在UART 接收器空闲时,如果数据输入变成“低电平”,即接收到了起始位,则接收计数器开始运行,并且数据在Baud16 的第8 个周期被采样。如果Rx 在Baud16 的第8 周期仍然为低电平,则起始位有效,否则会被认为是错误的起始位并将其忽略。  如果起始位有效,则根据数据字符被编程的长度,在 Baud16 的每第 16 个周期对连续的数据位(即一个位周期之后)进行采样。如果奇偶校验模式使能,则还会检测奇偶校验位。  最后,如果Rx 为高电平,则有效的停止位被确认,否则发生帧错误。当接收到一个完整的字符时,将数据存放在接收FIFO 中。  4. 中断控制  出现以下情况时,可使UART 产生中断:  FIFO 溢出错误  线中止错误(line-break,即Rx 信号一直为0 的状态,包括校验位和停止位在内)  奇偶校验错误  帧错误(停止位不为1)  接收超时(接收FIFO 已有数据但未满,而后续数据长时间不来)  发送  接收  由于所有中断事件在发送到中断控制器之前会一起进行“或运算”操作,所以任意时刻 UART 只能向中断产生一个中断请求。通过查询中断状态函数UARTIntStatus( ),软件可以在同一个中断服务函数里处理多个中断事件(多个并列的if 语句)。  5. FIFO 操作 FIFO 是“First-In First-Out”的缩写,意为“先进先出”,是一种常见的队列操作。 Stellaris 系列ARM 的UART 模块包含有2 个16 字节的FIFO:一个用于发送,另一个用于接收。可以将两个FIFO 分别配置为以不同深度触发中断。可供选择的配置包括:1/8、 1/4、1/2、3/4 和7/8 深度。例如,如果接收FIFO 选择1/4,则在UART 接收到4 个数据时产生接收中断。  发送FIFO的基本工作过程: 只要有数据填充到发送FIFO 里,就会立即启动发送过程。由于发送本身是个相对缓慢的过程,因此在发送的同时其它需要发送的数据还可以继续填充到发送 FIFO 里。当发送 FIFO 被填满时就不能再继续填充了,否则会造成数据丢失,此时只能等待。这个等待并不会很久,以9600 的波特率为例,等待出现一个空位的时间在1ms 上下。发送 FIFO 会按照填入数据的先后顺序把数据一个个发送出去,直到发送 FIFO 全空时为止。已发送完毕的数据会被自动清除,在发送FIFO 里同时会多出一个空位。  接收FIFO的基本工作过程: 当硬件逻辑接收到数据时,就会往接收FIFO 里填充接收到的数据。程序应当及时取走这些数据,数据被取走也是在接收FIFO 里被自动删除的过程,因此在接收 FIFO 里同时会多出一个空位。如果在接收 FIFO 里的数据未被及时取走而造成接收FIFO 已满,则以后再接收到数据时因无空位可以填充而造成数据丢失。  收发FIFO 主要是为了解决UART 收发中断过于频繁而导致CPU 效率不高的问题而引入的。在进行 UART 通信时,中断方式轮询方式要简便且效率高。但是,如果没有收发 FIFO,则每收发一个数据都要中断处理一次,效率仍然不够高。如果有了收发FIFO,则可以在连续收发若干个数据(可多至14 个)后才产生一次中断然后一并处理,这就大大提高了收发效率。  完全不必要担心FIFO 机制可能带来的数据丢失或得不到及时处理的问题,因为它已经帮你想到了收发过程中存在的任何问题,只要在初始化配置UART 后,就可以放心收发了, FIFO 和中断例程会自动搞定一切。  6. 回环操作  UART 可以进入一个内部回环(Loopback)模式,用于诊断或调试。在回环模式下,从Tx 上发送的数据将被Rx 输入端接收。  7. 串行红外协议  在某些 Stellaris 系列 ARM 芯片里,UART 还包含一个 IrDA 串行红外(SIR)编码器/ 解码器模块。IrDA SIR 模块的作用是在异步UART 数据流和半双工串行SIR 接口之间进行转换。片上不会执行任何模拟处理操作。SIR 模块的任务就是要给UART 提供一个数字编码输出和一个解码输入。UART 信号管脚可以和一个红外收发器连接以实现IrDA SIR 物理层连接。  如图所示,为UART 的IrDA SIR 模块基本应用电路。D1 为红外发射管,Q2 为红外接收管。  UART的基本结构及端口介绍  ⑴输出缓冲寄存器,它接收CPU从数据总线上送来的并行数据,并加以保存。  ⑵ 输出移位寄存器,它接收从输出缓冲器送来的并行数据,以发送时钟的速率把数据逐位移出,即将并行数据转换为串行数据输出。  ⑶ 输入移位寄存器,它以接收时钟的速率把出现在串行数据输入线上的数据逐位移入,当数据装满后,并行送往输入缓冲寄存器,即将串行数据转换成并行数据。  ⑷ 输入缓冲寄存器,它从输入移位寄存器中接收并行数据,然后由CPU取走。  ⑸ 控制寄存器,它接收CPU送来的控制字,由控制字的内容,决定通信时的传输方式以及数据格式等。例如采用异步方式还是同步方式,数据字符的位数,有无奇偶校验,是奇校验还是偶校验,停止位的位数等参数。  ⑹状态寄存器。状态寄存器中存放着接口的各种状态信息,例如输出缓冲区是否空,输入字符是否准备好等。在通信过程中,当符合某种状态时,接口中的状态检测逻辑将状态寄存器的相应位置“1”,以便让CPU查询。

编辑本段软件UART的设计思想

  数据发送的思想是,当启动字节发送时,通过TxD先发起始位,然后发数据位和奇偶数效验位,最后再发停止位,发送过程由发送状态机控制,每次中断只发送1个位,经过若干个定时中断完成1个字节帧的发送。  数据接收的思想是,当不在字节帧接收过程时,每次定时中断以3倍的波特率监视RxD的状态,当其连续3次采样电平依次为1、0、0时,就认为检测到了起始位,则开始启动一次字节帧接收,字节帧接收过程由接收状态机控制,每次中断只接收1个位,经过若干个定时中断完成1个字节帧的接收。  为了提高串口的性能,在发送和接收上都实现了FIFO功能,提高通信的实时性。FIFO的长度可以进行自由定义,适应用户的不同需要。  波特率的计算按照计算公式进行,在设置最高波特率时一定要考虑模拟串口程序代码的执行时间,该定时时间必须大于模拟串口的程序的规定时间。单片机的执行速度越快,则可以实现更高的串口通讯速度


评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值