题目类型:
- 单选题(10 x 5’ = 50’)
- 多选题(8 x 7’ = 56’)【错选不得分,少选得1/3分】
- 填空题(1 x 5’ = 5’)
文章目录
- 单选题
-
- 1、systemverilog语法中以下哪种写法是packed array
- 2、Which of the following metal layer has Maximum resistance?
- 3、下列哪个选项可以最大限度的提高ASIC的工作频率
- 4、7nm工艺中的7nm指的是()
- 5、Choose the correct equation for power calculation()
- 6、uvm中以下哪个phase是不需要消耗耗仿真时间的的?
- 7、下列关于多 bit 数据跨时钟域的处理思路,错误的有
- 8、(图文)There is a REQ-ACK interface following below protocol diagram.
- 9、下面哪项检查不属于版图物理验证:
- 10、For a truth table like below, which kind of logic cell could it be?
- 多选题
-
- 1、Which can be used to convert std::string to char array `std::string str = "Hello world"` -> `char cstr[str. size()+ 1]` (multiple answer)
- 2、未来AI处理器的演进有可能走如下哪些方向?
- 3、Select which grep command can be used to match ASClI string '*enflame-tech*X' where X is any integer number (multiple answer)
- 4、Please select correct statements for below 2 types of design (multiple answer)
- 5、Which are correct start point candidates in STA for data path (multiple answer)?
- 6、下列哪些问题不属于硬件架构性能评估范畴?
- 7、关于验证需盖率,以下说法正确的是
- 8、理想情况下,下列条件有利于满足Flip-Flop的建立时间的是:
- 填空题
单选题
1、systemverilog语法中以下哪种写法是packed array
【A】int array [0:7] [0:31]
【B】bit [7:0] array [0:31]
【C】bit [31:0] [7:0] array
参考答案:C
解析:略。
2、Which of the following metal layer has Maximum resistance?
【A】Meta13.
【B】Meta18.
【C】Meta15.
【D】Meta12.
参考答案:B