Cache mapping techniques

Cache mapping technique can be divided into three parts.
In order to show this three ways simplely, I use examle of library for anology.
Cache can somehow be part of memory of computer, instead of main memory, cache is smaller and can extract or load data quicker than main memory.
Assume main memory is the total number of books store in Leavey, then cache is (a) book shelf(ves), we extract books from leavey and put it on the shelf. So we need some mechanism to match the book which we take from the Leavey and where to put on the shelf. Still consider the word match , in computer system the only way to find out whether two items or more are same is compare, in hardware is comparator.

So, here we should keep in mind there are two things important in cache mapping. First mapping mechanism ---- how cache extract or load data from or to main memory. Second comparator — how to find out this is the data part Cache or main memory needs.
Let me introduce three mapping ways.

Assume Leavey has 10million books, a book shelf has 1000 slots. Then we can divide book’s ISBN 0123456789 to two parts, higher 7 units are wrapper name, lower 3 units are slot name. The wrapper name is a token decides which shelf the books belong to, and slot name decides which slot or which place of the shelf the book should be placed. Just mod ISBN with 1000, we get the slot name, similarly we get wrapper name.

1. Fully-associative
   This mechanism is the most easy way of mapping techniques. Consider byte-addressable processor has 64-bit data and 32-bit address. There will be 4 banks and each bank is 8-bit in the MM. So 3 address line is needed to match each address. If the cache block size is 2 words, only 1 address line is needed to decide which word is.
   So here we need 4 address lines to decide a word which similar to the space each book needs. The upper address line (A31-A4) then put into TAG FIELD to decide which shelf the books belong to.
2. Direct

Look back to Fully-associative way, in order to deicde which shelf we need comparator for each SET FIELD, which is not efficient. So Direct solves this problem. Also 4 bit wide address for a word, Dircet mapping divede cache into many blocks. Assume cache size is
512KB, then there will be 2^15 blocks because each 2 words occupy 2*8 bytes. Then TAG FIELD will be 13 bit wide to decide which SET FIELD data belongs to. Here we only need one 13 bit comparator to compare TAG name, then data can be poperly located.

3. Set-associative

Direct mapping need less comparator than Full-associative. But there is one problem cannot be solved. COLLISION. What if two datas have the same SET FIELD number? Take ISBN for example, what if book A ISBN is 0123456789 and B ISBN is 0123455789, both last three bits are same, then put them into same book shelf and same slot? Apparently, this is not right and can cause collision. (This situation is frequently shown when code address and data address in MM have same last few bits and extract this two different data into cache will cause collision.) In order to avoiding this, set-associative maping is introduced.
We can divide Block set into 2 or 4 or 8 as you wanted. This Block set means the same shelf but not exactly the same. Book A store in shelf S1 which TAG name is T, book B store in shelf S2 which Tag name is T. So if you have 4 block sets, then 2 bit address lines are needed, then the TAG FIELD is 13 bit left.