CPU设计实战 lab3

Lab3

题目说Lab3有七处错误，我怀疑Mistake 5或者Mistake 8是原本就有的，作者没发现的问题

Mistake 1

Run Simulation后发现debug_wb_pc的值一直为XXXXXXXX,向前溯源可以发现原因出在了ID_stage中，未对ds_valid进行赋值，然后一直影响到debug_wb_pc的值

修改前:

always @(posedge clk) begin
    if (fs_to_ds_valid && ds_allowin) begin
        fs_to_ds_bus_r <= fs_to_ds_bus;
    end
end

修改后代码:

always @(posedge clk) begin
    if (reset) begin
        ds_valid <= 1'b0;
    end
    else if (ds_allowin) begin
        ds_valid <= fs_to_ds_valid;
    end

    if (fs_to_ds_valid && ds_allowin) begin
        fs_to_ds_bus_r <= fs_to_ds_bus;
    end
end

Mistake 2

ID_stage中，load_op未赋值，为Z

assign load_op      = inst_lw;

Mistake 3

EXE_stage中，alu_src1连接到es_alu_src2了

alu u_alu(
    .alu_op     (es_alu_op    ),
    .alu_src1   (es_alu_src2  ),
    .alu_src2   (es_alu_src2  ),
    .alu_result (es_alu_result)
    );

Mistake 4

br_bus位宽为32,导致br_taken恒为0，无法选择branch,将BR_BUS_WD改为33即可

wire [ 31:0] br_target;
assign {br_taken,br_target} = br_bus;

    `define BR_BUS_WD       33

Mistake 5

MEM_stage中，对es_to_ms_bus_r使用是阻塞赋值，改为非阻塞赋值

    if (es_to_ms_valid && ms_allowin) begin
        es_to_ms_bus_r <= es_to_ms_bus;
    end

Mistake 6

alu中存在循环赋值

assign or_result  = alu_src1 | alu_src2 | alu_result;

assign alu_result = ({32{op_add|op_sub}} & add_sub_result)
                  | ({32{op_slt       }} & slt_result)
                  | ({32{op_sltu      }} & sltu_result)
                  | ({32{op_and       }} & and_result)
                  | ({32{op_nor       }} & nor_result)
                  | ({32{op_or        }} & or_result)
                  | ({32{op_xor       }} & xor_result)
                  | ({32{op_lui       }} & lui_result)
                  | ({32{op_sll       }} & sll_result)
                  | ({32{op_srl|op_sra}} & sr_result);

修改后:

assign or_result  = alu_src1 | alu_src2;

Mistake 7

alu中，给sr_result赋值的位宽错误

assign sr_result   = sr64_result[30:0];

修改后:

assign sr_result   = sr64_result[31:0];

Mistake 8

这里是在Bunny9__的文章中知道的

tools.v文件中，生成6-64 decoder时循环终止条件写错

genvar i;
generate for (i=0; i<63; i=i+1) begin : gen_for_dec_6_64
    assign out[i] = (in == i);
end endgenerate

修改后:

genvar i;
generate for (i=0; i<64; i=i+1) begin : gen_for_dec_6_64
    assign out[i] = (in == i);
end endgenerate