- von Neumann architecture:
- Data and instructions are stored in a single read-write memory
- The contents of this memory are addressable by location, without regard to the type of data contained there
- Execution occurs in a sequential fashion(unless explicitly modified) from one instruction to the next
- Computer main components
- CPU
- I/O
- Main memory
- System bus
- Computer function
- Basic function performed by a computer is execution of a program
- The CPU time of processing an instruction is called instrucion cycle.
- Instruction processing consists of two steps: The processor reads(fetches) instrctions from the memory one at a time and executes each instrction.
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- instruction cycle = fetch cycle & execute cycle
- Instruction fetch and execute
- The processot fetches an instruction from memory
- Unless told otherwise, the processor always increments the PC after each instruction fetch.
- Length of PC should be calculated, however, it, in fact, equals to the length of AC/IR
- The fetched instruction is loaded into a register in the processor known as the instruction register(IR)
- The processor interprets the instruction and performs the required action:
- Data transfer between CPU and main memory
- Data transfer between CPU and I/O module
- Some arithmetic or logical operation on data
- Control
- Combination of above
- Flow of an Instruction
- Instruction address calculation
- Instruction fetch
- Instruction operation decoding
- operand address calculation
- Operand fetch
- Data operation
- Operand storage
- Interrupts: a mechanism allowing other module to break CPU executing sequence
- To improve processing efficiency
- To allow CPU to process urgent events
- If interrupt is pending, the processor does the following:
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- Suspend execution of the current program being executed andsave its context
- Save current context of PC and other data
- Set the PC to starting address of an interrupt handler routine
- An interrupt cycle is added to instruction cycle
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- After an instruction cycle,processor checks for interrupt, Indicated by an interrupt signal
- If no interrupt, fetch next instruction
- If interrupt :
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- Suspend execution of current program
- Save context
- Set PC to start address of interrupt handler routine
- Process interrupt
- Restore context and continue interrupted program
- Multiple interrupts: an interrupt handler is interrupted
- Disable interrupts
- Easy, FIFO
- Define priorities
- More common
- Disable interrupts
- I/O function
- An I/O module can exchange data directly with the processor
- In some cases, it is desirable to allow I/O exchanges to occur directly with memory---DMA
- Interconnection structure
- The collection of paths connecting the various modules is called the interconnection structure
- Bus interconnection
- A bus is a communication pathway connecting two or more devices(shared transmission medium)
- Bus type
- System bus: A bus that connects major computer components is called a system bus
- Peripheral bus
- Internal bus
- Data bus: for moving data between system modules
- The width of the data bus is a key factor in determining overall system performance
- Machine word-length: The most binary bits which machine can process in the integer operation
- Data bus width = Machine word-length = Register length
- Address bus: designate the source or destination of the data on the data bus
- The width of the address bus determines the maximum possible memory capacity of the system
- Control line: to control the access to and the use of the data and address line
- Memory read/write signal
- I/O read/write
- Transfer ACK
- Bus Request
- Bus grant
- Interrupt request & ACK
- Clock signals
- Reset
- Multiple-bus hierarchies
- If great number of devices are connected to the bus, performance will suffer
- greater bus length → greater propagation delay
- Bottleneck
- If great number of devices are connected to the bus, performance will suffer
- Elements of bus design
- Bus types
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- Dedicated
- Advantage: high throughput
- Disadvantage: scale and cost increases
- Multiplexed
- Advantage: fewer lines → saves space and cost
- Disadvantage: more complex control, potential reduction in performance
- Dedicated
- Method of bus arbitration: more than one module may need control of the bus
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- Centralized: a single hardware device, referred to as a bus controller or arbiter, is responsible for allocating time on the bus. The decive may be a separate module or part of the processor
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- Daisy chain polling
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- Advantage: scalable
- Disadvantage: sensitive to circult failure
- Counter polling
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- Advantage: flexible priority, insensitive to circuit failure
- Disadvantage: complex control
- Separate request
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- Advantage: rapid response, flexible priority
- Disadvantage: too many lines, complex comtrol
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- Distributed: there is no central controller. Each module contains access control logic and the modules act together to share the bus
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- Timing: the way in which events are coordination on bus
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- Synchronous: the occurrence of events is determined by clock signals
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- Advantage: simple, easy to implement
- Disadvantage: inflexible, velocity based on the slowest module(bottleneck)
- Asynchronous: the occurrence of one event on a bus follows and depends on the occurrence of a previous event
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- Advantage: request-responce, allowing fast and slow devices
- Disadvantage: complex control
- Types of asynchronous communication
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- Half-synchronous
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- Clock is needed
- Wait line is needed
- Allowing various speed modules to communicate harmoniously
- Used for connecting low speed and larger speed difference devices
- Separate
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- Basic idea is:
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- Separate bus cycle into two sub-cycles
- In the first sub-cycle, master puts command, address and other information into the bus, then abandons the bus
- In the second sub-cycle, slave begins to prepare data (select, decode, load), then applies the bus and sends the data
- Advantage: avoiding bus idle waiting
- Used for large computer
- Bus width ≠ Bus bandwidth
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- The width of data bus has an impact on system performance
- The width of address bus has an impact on system capacity
- Data transfer type
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