- It is unlikely that the more stages in the pipeline, the faster the execution rate:
- At each stage, there are some overhead involved in moving data from buffer to buffer and in performing various preparation and delivery function.
- The more stages, the more complex control logic circuits.
- Processer organization
- Steps: need ALU, CU, registers
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- Fetch instructions
- Interpret instructions
- Fetch data
- Process data
- Write data
- Register organization
- The registers in the CPU serve two functions:
-
- User-visible registers
-
- Programmer can use these registers to reduce accessing main memory
- Categories:
-
- General purpose
-
- True general purpose
- Restricted
- Used for data or addressing
- Data
-
- Accumulator
- Address
-
- Segment pointers, index registers, stack pointers
- Condition codes
-
- Bits set by CPU hardware as the result of the last operations
-
- COAPZS
-
- positive, negative, zero, overflow ...
- Can be read implicitly by programs
- Usually cannot be set by programs
- Partially visible to programmers
- Design issues:
-
- Make them general purpose
-
- Pro: Increasing flexibility and programmer options
- Cons: Increasing instruction size and complexity
- Make them specialized
-
- Pros: Smaller instructions
- Cons: Less flexibility
- Control and status registers
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- Used by CU and privileged program(OS) to control the execution of users' program
- Four sorts for instruction execution
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- PC
- IR
- MAR: connected to address bus
- MBR: connected to data bus
- Instruction cycle
- Indirect addressing cycle
-
- May require memory access to fetch operands
- Indirect addressing requires more memory accesses
- Data flow(Instruction fetch)
-
- Fetch:
-
- PC contains address of next instruction
- Address moved to MAR
- Address placed on address bus
- Control unit requests memory read
- Result placed on data bus, copied to MBR, then to IR
- Meanwhile PC incremented by "1"
- Data flow(Indirect fetch)
-
- If indirect addressing is perfromed, indirect cycle is performed
-
- Right most N bits of MBR transferred to MAR
- Control unit requests memory read
- Result (address of operand) moved to MBR
- MBR→IR
- Data flow(Execute)
-
- Depends on how instruction being executed
- May include
-
- Memory read/write
- Input/Output
- Register transfer
- ALU operations
- Data flow(Interrupt)
-
- Current PC saved to allow resumption after interrupt
-
- Content of PC copied into MBR
- Special memory location loaded into MAR
- PC loaded with address of interrupt handling routine
- Instruction pipelining ----> improve performance
- Pre-fetch: can fetch next instruction during decoding and execution of current instruction
- An instruction has a number of stages: nearly equal duration
-
- Fetch instruction
- Decode instruction
- Calculate operands address
- Fetch operands
- Execute instructions
- Write operands
- Specifications
-
- Assuming that there is no conflicts and dependencies
- If are not of equal duration, short stages must wait
- Condition branch and interrupt will reduce the performance of pipeline
- Pipeline performance
-
- Dealing with branches
- Multiple Streams
-
- Have two pipelines
- Pre-fetch each branch into a separate pipeline
- Limits
-
- Leads to bus & register contention
- Multiple branches lead to further pipelines being needed
- Pre-fetch Branch Target
-
- Target of branch is pre-fetched in addtion to instructions following branch
- Keep target until branch is executed
- Loop buffer
-
- A small, very fast memory containing n most recently fetched in sequence instructions
- If a branch is to be taken, the hardware first checks buffer before fetching from memory
- Good for small loops
- Branch prediction
-
- Predict never taken: always fetch next instruction
- Predict always taken: always fetch target instruction
- Predict by Opcode: can get up to 75% success
- Taken/Not taken switch: based on previous history
- Branch history table/Branch target buffer
- Delayed branching
-
- Insert NULL operations
- Rearrange instructions
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- Out-of-order execution
Chapter 12 CPU Structure and Function
最新推荐文章于 2022-04-24 11:26:27 发布