part 3 Cache Memory 3

Direct -Mapping Cache Organization (The transaction among cpu, cache and main memory)

Memory address is consist of three parts: Tag, line and word.

For example, the line is r bits, the word is w bits. tag and line is s bits.

Then the Address length is (s+w)bits

number of addressable units is 2^(s+w) words or bytes

size of the tag is (s-r)bits

block size is the line size that is 2^w words or bytes

number of block in main memory is  2^(s+w)/2^w, that is 2^s

number of line in cache is m=2^r

size of the cache is 2^(r+w) words or bytes.

not clear yet