TDA4框图解析

按照从左到右，从上到下的方式介绍模块：

先介绍Core相关的模块，

Dual-Core Cortex A72 with MPU  L2 Cache 1MB            x 1

Quad-Core Cortex R5F   TCM 64KB                                x 2

Dual-C66x DSP   32KB SRAM + L2 Cache 256KB          x 1

C71 with Matrix Multiplication Accelerator  L2 Cache 512KB       x  1

这里要注意，A核与R核的Cache是不同的架构。

然后是存储模块MSMC(multi Core Shared Memory Controller)

含有1x DRU(Date Routing Unit) +CMMU 内部还含有4MB SRAM with ECC

DDRSS 内部包含 2x 32b =64 b总线，同时含有In-Line ECC 功能 和MFLAG。

The Data Routing Unit (DRU) is a high bandwidth, flexible routing engine with programmable DMA transfer requests which enables performing of high speed data transfers between memory mapped slave endpoints,processor caches and shared caches. It behaves like a DMA transfer controller, moving data at MPU frequency and has the following main features:
• Programmable configuration registers for direct transfer request submission
• Read and write command queues
• Programmable priority for each queue
• Two dedicated ports (one read and one write) to generate independent read and write commands
• Support for region based and channelized firewall
• Independent 48-bit address fields for source and destinations
• Up to four dimensional data transfers
• Error detection and Correction

The CorePac Memory Management Unit (CMMU) extends the C71x architecture with support for address translation, access permission and protections and memory attributes determination and checking. It is implemented per C71x cluster as a two-level TLB structure. The CMMU works with the C71x L1 caches, stream buffers in each processor and CorePac memory system of CorePac cluster to translate virtual addresses to physical addresses, controls tablewalk hardware that accesses translation tables in main memory. The CMMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory
attributes held in the L1 level micro translation look-aside buffer (uTLB) and CorePac cluster level translation look-aside buffers (TLBs).

左侧从上到下，H264/5的编解码模块；CTRL_MMR是TDA4的模块配置信息的寄存器；DeBugSS 是用于 DeBug的模块；PLL 和TIMER不做介绍；WWDT是窗口看门狗；

NAVSS 是导航子模块，用于Linux 内核的功能支持。

其他模块介绍如下：

PSC Power Sleep Controller

VPAC 是 Vision Pre-processing Accelerator，用于处理视觉信息处理加速，HDR,WDR，Color Processing等。

DMPAC 是Depth and Motion Perception Accelerator 主要也是用于视觉的，处理立体光流场。

The Depth and Motion Perception Accelerator (DMPAC) computes dense stereo depth maps (depth) and dense optical flow vectors (motion) from camera inputs. The stereo and optical flow processing is partitioned into two top level sub-blocks: the Dense Optical Flow (DOF) engine and the Stereo Disparity Engine (SDE). The DOF and SDE blocks share a common local memory, DMA, external messaging and control infrastructure. The DMPAC provides the following main features, among others:

还有 ATL(Audio Tracking Logic) 和MCASP(Multichannel Audio Serial Port) 均是用于音频处理的模块，AES-3,P/DIF等是特殊的音频格式。

AES/SHA/DES/PKA/3DES/RNG+DRBG 均是加密算法。

Video Processing Front End (VPFE) is an input interface module that receives raw (unprocessed) image/video data or YUV digital video data from external imaging peripherals (such as image sensors, video decoders, etc.) and performs DMA transfers to store the captured data in the system DDR memory.
CPSW是 Comman Platform Ethernet Switch的简称，CPSW为三端口调换器（three port switch ），一个cpu端口，两个外部端口。CPSW或者说以太网调换驱动遵循标准的Linux网络接口构造。