Cadence招聘数字后端产品验证工程师

最新推荐文章于 2021-06-10 10:41:53 发布

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最新推荐文章于 2021-06-10 10:41:53 发布

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1. Product Validation Engineer II

Position Description:

 This engineer will work in Encounter block implementation product validation team. The responsibilities include:

 Assist in Cadence EDI development and validation Validate and maintain comprehensive unit and flow test cases for Encounter Digital Implementation System.

 Develop test suites of the new features of EDI functions

Position Requirements:

 MS of EE/CS

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

2. Product Validation Engineer II

Position Description:

 This engineer will work in Encounter Router product validation team. The responsibilities include:

 Assist in Cadence EDI development and validation Validate and maintain comprehensive Router unit and flow test cases for Encounter Digital implementation System.

 Develop test suites of the new features of EDI Router function

Position Requirements:

 MS of EE/CS

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

3. Lead Product Validation Engineer

Position Description:

 This engineer will work in Encounter clock product validation team. The responsibilities include:

 Assist in Cadence EDI developement and validationValidate and maintain comprehensive clock unit and flow test cases for Encounter Digital Impelementation System.

 Develope testsuites of the new features of EDI clock function

Position Requirements:

 MS of EE/CS with 2+ work experience

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus.

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

4. Lead Product Validation Engineer

Position Description:

 Assist in Cadence hierarchical flow development and validation

 Validate and maintain comprehensive hierarchical unit and flow test cases for Innovus Digital Implementation System.

 Develop test suites of the new features of hierarchical functional/flow solution

Position Requirements:

 MS or excellent undergraduate with 2 years experiences

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

5. Lead Product Validation Engineer

Position Description:

 Identify timing sign-off challenges in complex SOC designs and the correlation issues between preRoute & postroute in advacned process nodes

 Proactively provide STA & extraction development suggestions to R&D.

 Build up extraction & STA expertise and deliver support to field team and customers whenever needed.

 Required to acquire expertise and ownership over existing product components as well as develop brand new product features.

Position Requirements:

 Bachelor with 5 years related experience or Master with at least 3 years related experience in design house, FAB or EDA company.

 Rich experience in IC design flow (front-end or back-end).

 Experience in parasiticis extraction, or knowledge in timing closure is a strong plus.

 Good Unix System knowledge and script skill of TCL/TK/CSH/PERL.

 Excellent capability of self-learning, problem solving skills;

 Being proactive and self-motivated;

 strong leadership;

 Good written English and oral English is a strong plus

6. Product Validation Engineer II

Position Description:

This PV engineer mainly works for advanced STA (Static Timing Analysis) and

DelayCal features validation:

 Qualify delay calculation and timing analysis result in Innovus system;

 Maintain comprehensive regression suites for monitoring STA & delayCal stabilities;

 Upgrading regression cases to use advanced design node data and check the impact;

Position Requirements:

 Master degree or bachelor degree with 2~3 years working experience;

 Solid background knowledge in digital backend design, knowledges in STA or delayCal is a strong plus;

 Be familiar with Linux system, and scripting skills with TCL or PERL or Shell;

 Patient, and good responsibilty;

 Good communication in Englist and Chinese.

7. Computational Lithography Solutions Lead Product Validation Engineer

Position Description:

 Computational Lithography Solutions (CLS) is part of Digital & Signoff Group in Cadence Design Systems. Main products include optical proximity correction (OPC), process modeling, and OPC verification. We have customers located in US, Europe, and Asia.

 We are looking for self-driven individual to join our product engineering (PE) group as Lead Product Validation Engineer, and be located in Pudong office in Shanghai, China. Responsibilities for this position includes product ownership, preparing documentation, conducting quality assurance, product testing, and interfacing with R&D Team in San Jose, CA.. And, the prospective employee will be reporting to San Jose, CA office.

Position Requirements:

 Self-driven and quick learner individual with strong analytical and problem solving skills.

 Attention to the details, and being comfortable with writing documentation

 Strong interpersonal and communication skills

 Working knowledge of speaking and writing English

 Bachelor of Science or Master of Science in Engineering or technical field.

 Experience with OPC software or another electronic design automation (EDA) software is preferred but not required. Recent graduates are welcomed to apply.

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