产品工程师验证工程师

最新推荐文章于 2022-06-17 10:59:38 发布

Tao_ZT

最新推荐文章于 2022-06-17 10:59:38 发布

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产品工程师

1. Principal Customer Engagement Engineer -Synthesis

Position Description:

 The primary responsibility is designing, developing, troubleshooting and debugging software programs on Unix/Linux platforms.

 Will be involved in developing software tools for advanced chip design platforms.

 The responsibilities also include engaging with customers in understanding their ASIC design requirements for nano-technology process nodes and assisting them in adopting Cadence design platform and helping them in performing successful tapeouts of their System-on-chip designs using the same.

 The job will also involves presenting and demonstrating relevant Cadence technologies and carrying out product evaluations, workshops, trainings and competitive replacement campaigns.

Position Requirements:

 The candidates should have strong in-depth RTL synthesis experience in COT or ASIC area.

 Experience and ability to get solutions in RTL Generic/Mapping as well as Phyiscal-aware synthesis is a MUST.

 Strong experience in timing analysis, sdc processing and understanding are also required.

 Need to have good knowledge on VDSM (40nm and below) processes issues.

 Good verbal and written presentation are must.

 Hands-on Cadence Synthesis experience will a big plus.

 Minimum master degrees in EE or CS.

2. Product Engineer

Position Description:

 Work in shanghai Silicon Signoff and Verification (SSV) electrical PE team, focus on Voltus Power System (Voltus).

 Support key customer engagements and local AEs to help on the business increase.

 Working as a domain expert to well communicate with customers for their valuable feedbacks

 Co-work closely with R&D team to enhance the tool based on customers' real demanding

Position Requirements:

 Electrical analysis experience is necessary, IC level or system level power related analysis will be desired, e.g. Cadence Power System, Redhawk, Totem, Sigrity.

 Working experience with foundry and process tech files, spice models are desired

 Product Engineering and customer supporting experience is desired.

 Good communication in English and Chinese, good confidence and good self-motivation.

3. Principal Solutions Engineer, HSV R&D

Position Description:

This position is for HSV SWAT team. SWAT team belongs to HSV RD, and is in

charge of:

 Support: support the key account and key engagement in the local area that team member is located.

 Explore: explore user's need and take the feedback back to BU

 Validate: Validate and deploy the new technology on site, including the knowledge transfer to local team

 The focus on the technical aspects includes:

 Cadence HW Acceleration Platforms and related solution especially SW HW co-verification and system level verification

 Cadence Acceleration Verification IP portfolio

 HSV product integration with other Cadence products such as Incisive Simulation and RTL Compiler for power analysis

Position Requirements:

 SW HW Co-verification, means either the RTL design and verification knowledge, or the experience of firmware, OS, driver development in IC design firms.

 A good knowledge of RTL design and verification tools (HDLs, synthesis tools, design simulation, acceleration using emulators) or the firmware development tools.

 Good understand on the challenge of SoC verification

 ESL knowledge is a very great plus

 Previous knowledge and hands on experience of emulation project is a great plus

 System Verilog and UMV methodology is a great plus

 Knowledge of at least one popular script language such as, Perl, Shell, Tcl, or C

 Ideally the person should possess the BS/BE level of understanding of EE Engineering concepts

 Minimum Education Required: education level of BS with 10+ years’ experience (or MS with 7+ or more years’ experience).

验证工程师

1. Lead PV Engineer -Sigrity and Allegro PCB SI

Position Description:

Introduction

 We are looking for a signal integrity engineer with 1-5 years of experience in High Speed design. You will be responsible for testing and overseeing the quality management of our family of software products that deal with SI design.

Duties

 You will work within a global multi-functional team to review project plans and functional specifications, develop test criteria and written test plans, manually exercise and test functionality of the Allegro PCB SI and Sigrity products and develop automated tests within the existing test environment. As this position requires a good understanding of the signal integrity knowledge. You will maintain regression tests and evaluate results on a regular basis.

Position Requirements:

Requirements

 BS Degree is required, MS is preferred

 Working experience with the Sigrity tools is strongly desired

 Solid understanding of the following: signal integrity, modeling and simulation

 Recent experience with signal integrity tool is a must

 Knowledge of other PCB design, routing, and packaging is a plus

Experience

 Knowledge of Windows and Linux platforms is essential

 Any experience in software validation

 Programming knowledge in Perl is strongly desired

 Experience with an error tracking and reporting product is valuable

Basic Abilities

 Strong written and verbal communication skills, in English and Chinese are mandatory as the candidate will be interacting with a global team based in the US and China.

 Ability to follow a schedule is essential

 Familiarity with software development life cycle is a plus

 Ability to detect, report and explain defects effectively is crucial

 Possess good analytical, problem solving skills

 Understand test processes and methodologies in a software development environment

 Self-starter, self-sufficient, able to work independently as well as with teams, able to multitask

2. Lead Design Engineer--Memory Modeling Portfolio

Position Description:

 Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products. Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products. Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP. Interface with internal and external customers to work on diverse problems and

solutions related to emulation, simulation, or verification. Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.

Position Requirements:

 The position requires BSEE, or equivalent, with a minimum of 4 years of industry experience in designing hardware systems. Must have excellent communication skills with both written and spoken English. RTL design knowledge using Verilog/System Verilog is required along with experience using RTL verification tools and flows. Debugging experience. Experience with team-wide collaboration tools and process. Drive and ability to schedule workload and plan own tasks effectively.

 Strongly recommended: Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. Experience in memory sub-system design and operation is strongly recommended.

3. Lead Design Engineer--FPGA

Position Description:

 Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.

Position Requirements:

 The position requires BSEE, or equivalent, with a minimum of 4 years of industry experience in designing hardware systems.

 Must have excellent communication skills, both written and verbal.

 Technical expertise in FPGA design for either Altera or Xilinx products is required.

 Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired. In addition RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows. Verification using with Cadence simulation products is desired. Experience with scripting languages like Perl, TCL C-shell is strongly recommended. Experience with PCB tools is also desired.

4. Product Validation Engineer II

Position Description:

 This engineer will work in Encounter block implementation product validation team. The responsibilities include:

 Assist in Cadence EDI development and validation Validate and maintain comprehensive unit and flow test cases for Encounter Digital Implementation System.

 Develop test suites of the new features of EDI functions

Position Requirements:

 MS of EE/CS

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation

5. Product Validation Engineer II

Position Description:

 This engineer will work in Encounter Router product validation team. The responsibilities include:

 Assist in Cadence EDI development and validation Validate and maintain comprehensive Router unit and flow test cases for Encounter Digital implementation System.

 Develop test suites of the new features of EDI Router function

Position Requirements:

 MS of EE/CS

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

6. Product Validation Engineer II

Position Description:

 Assist in Cadence hierarchical flow development and validation

 Validate and maintain comprehensive hierarchical unit and flow test cases for Innovus Digital Implementation System.

 Develop test suites of the new features of hierarchical functional/flow solution

Position Requirements:

 MS or excellent undergraduate with 2 years experiences

 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus

 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.

 Good communication in English and Chinese, good confidence and self-motivation.

7. Lead Product Validation Engineer

Position Description:

 Cadence ICD Product Validation Regression system is the core system infrastructure of the whole Product Validation organization, which can greatly improve the whole organization's efficiency and boost the team productivity.

 This position is responsible for the regression system and application development and maintenance.

 The candidate need use all kinds of knowledge and skills to design and improve the system based on the business requirement for the organization operation and the existing system and related software/hardware environment.

Detailed Responsibility:

 Analyze System and Business requirement, based on which design the system flow chart

 Do the needful system/scripts maintenance/improvement

 Communicate with related IT and PV team and drive to improve organization operation efficiency

 Innovate on the next generation system to boost organization's efficiency.

Position Requirements:

 Bachelor with 4 years related experience or Master with 2 years related experience

 Result driven and details focused working attitude

 Excellent analytical skills and complex system problem solving skills

 Strong technical experience in Unix/Linux usage

 Strong Perl/Tcl/Cshell scripting

 Good knowledge and experience in CGI programming