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各位好：
这是我的第一篇博客。是一篇在FPGA中利用Verilog代码实现去抖动的代码博客，希望对大家有用。
如有Bug和不足之处还望指出，谢谢。

//
// Company: SCU
// Engineer: YinyuLiu
//
// Create Date: 10:22:41 06/04/2015
// Design Name: CommonTools
// Module Name: Debounce
// Project Name: >>>> PublicParts
// Target Devices:
// Tool versions: Quartus II v9.1
// Description: >>>> This module is designed for common use of sliminate jitter of button.
// >>>> erveryone can use it and improvement it.
// Dependencies:
//
// Revision: 1.0
// Additional Comments:
// >> Caution: Only non-commercial use, reproduce, please indicate the
// >> source and author.
// >> SCU—->Particle Physics and Nuclear Physics—->LiuYinYu
// >> Liuyinyu0629@foxmail.com
// >> chengdu/China.
//
//
module Debounce(pulseIn, clk, pulseOut);

parameter ClkFrequency = 25;  //MHz
parameter Bit32 = 32;
parameter TimeDelay = 30; //ms
parameter TimeConstant = ClkFrequency*TimeDelay*1000;

input pulseIn;
input clk;
output pulseOut;

reg [Bit32-1:0] timeCount = 32'b0;
reg pulseOut;
reg pulse1,pulse0;
reg debouncing = 1'b0;

always @(posedge clk) 
begin
     pulse0 <= pulseIn;
    pulse1 <= pulse0;
    if (!debouncing)
    begin
        if(pulse1 == 1'b0 && pulse0 == 1'b1)
        begin
            debouncing <= 1'b1;
            pulseOut <= 1'b1;
        end
        else if(pulse1 == 1'b1 && pulse0 == 1'b0)
        begin 
            debouncing <= 1'b1;
            pulseOut <= 1'b0;
        end
    end
    else if (debouncing)
    begin
        if(timeCount < TimeConstant[Bit32-1:0])
            timeCount <= timeCount + 32'd1;
        else
        begin
            debouncing <= 1'b0;
            timeCount <= 32'd0;
        end
    end
end

endmodule