SWJTU计算机组成实验C-实验四 算术逻辑单元（ALU）设计

实验目的，实验目的，说明实验仪器、设备等说明参见《计算机组成实验C》实验及课程设计指导书

程序代码

8bit ALU设计：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

   PORT(INPUT_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       CTRL_S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       SEL, WT, CIN, CLK : IN STD_LOGIC;
       COUT : BUFFER STD_LOGIC;
       OUTPUT_F : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
       DIGITAL_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       SEG_SEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY ALU_8BIT;

ARCHITECTURE FRAME1 of ALU_8BIT IS
   SHARED VARIABLE REG_A, REG_B : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SHARED VARIABLE RECEIVE : STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL OUTPUT_SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL DA