翻译：XILINX文档ug474_7Series_CLB——Ch2.6 Shift Registers

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Shift Registers (Available in SLICEM Only)

A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data from 1 to 32 clock cycles. The shiftin D (DI1 LUT pin) and shiftout Q31 (MC31 LUT pin) lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM are thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers acrossmore than one SLICEM. There are no direct connections between slices to form longer shift registers, nor is the MC31 output at LUT B/C/D available. The resulting programmable delays can be used to balance the timing of data pipelines.

SLICEM可以在没有使用触发器的情况下，配置出一个32位的移位寄存器。因此，每一个LUT能够将每一个串行数据延迟1至32个时钟周期。通过将LUT的移位D（DI1 管脚）和移位Q31（MC31 管脚）进行级联，可以形成更大的移位寄存器。一个SLICEM的4个LUT6级联可以实现128个时钟周期的延时。也可以通过组合多个SLICEM来实现移位寄存器的扩展。但SLICEM之间没有直接连接以形成更长的移位寄存器，LUT B/C/D处的MC31输出也不可用。由此产生的可编程延迟可用于平衡数据管道的时间（时序）。

Applications for shift registers include:

• Delay or latency compensation

• Synchronous FIFO and content addressable memory (CAM)

移位寄存器的应用包括：
• 延迟或潜伏补偿
• 同步FIFO和CAM

Shift register functions include:

• Write operation

• Synchronous with a clock input (CLK) and an optional clock enable (CE)

• Fixed read access to Q31

• Dynamic read access

• Performed through the 5-bit address bus, A[4:0]

- The LSB of the LUT address is unused and the software automatically ties it to a logic High.

• Any of the 32 bits can be read out asynchronously (at the O6 LUT outputs, referred to as Q on the primitive) by varying the address

• This capability is useful in creating smaller shift registers (less than 32 bits).

- For example, when building a 13-bit shift register, set the address to the 13th bit.

• A storage element or flip-flop is available to implement a synchronous read.

- The clock-to-out of the flip-flop determines the overall delay and improves performan