xxx pro env some basic structures // thanks Dan~

// ーーーーーーーーーーーー
// Class: xxx_proj_env
// ーーーーーーーーーーーー
// Environment for the xxx_proj UVC

class xxx_proj_env extends uvm env;
	// Module UVC Config Objects
	// Object: xxx_proj cfg
	// Environment configuration object.
	xxx_proj_config xxx_proj cfg;

	// Object: xxx_proj_test_cfg
	// Test configuration object.
	xxx_proj_test_config xxx_proj_test_cfg;

	// Object: xxx_proj_dut_cfg
	// DUT configuration object (for parameterised/templated DUT)
	xxx_proj_dut_config xxx_proj_dut_cfg;

	//Objects: UVCs
	// Object: multi_clk_rst
	// Clock / reset UVC
	multi_clk_rst_master_agent multi_clk_rst;

	// Object: aes apb vip
	// APB interface for AES (VIP)
	xxx_proj_ext_svt_apb master agent/*svt_apb_master_agent*/ aes_apb_vip;

	// Object: aes apb vip reg adapter
	// Register adapter for aes apb vip
	xxx_proj_fips_apb_vip_reg_adapter  apb_vip_reg_adapter;

	// Object: caps regs wire reg adapter
	// Register adapter for accesses from the link. 
	xxxx_caps_regs_reg_adapter caps_regs_wire_reg_adapter;
	// Object: caps regs host reg adapter
	// Register adapter for accesses from the local host. 
	xxxx_caps_regs_reg_adapter caps_regs_host_reg_adapter;
	// Object: aes apb reg_ predictor
	// Predictor for register map
	uvm_reg_predictort(svt_apb_transaction) aes_apb_reg_predictor;
	// Object: config apb reg predictor
	// Predictor for register map
	uvm_reg_predictor#t (svt_apb_transaction) config_apb_reg_predictor;


	// Objects: UVC Configuration Objects
	multi_clk_rst_config multi_clk_rst_cfg;
	ide_data_config_tx plain_data_if_cfg[i];
	ide_data_config_tx secure_data_if_cfg[i]:
	ide_data_shared_config_tx_plain_data_shared_cfg;
	ide_tip_shared config_tx secure tip shared cfg; 
	ide_msg_config ide_msg_cfg;
	xxxx_caps_regs_config xxxx caps_ regs _cfg;
	aes_hw_config config aes_hw_config config
	// Object: regmodel
	// Register model for the xxxx IDE
	xxx_proj_regblk xxx_proj_regmodel;
	// Object:xxxx ide vsegr
	// Virtual Sequencer
	....

	// Function: Build Phase
	virtual function void build phase (um_phase phase) ;
		int nfm_max_tag;
		super.build_phase(phase);
	// -- Factory Overrides --
	// -- Register model --
	if (!uvm_config_db#(xxx_proj_regblk)::get(this, "", xxx_proj_regmodel", xxx_proj_regmodel)) begin
		uvm_fatal(get_type_name(), "xxx_proj_regmodel not set in config db")
	end
	// - -Module UVC config object - -
	if (!uvm_config_db.(xxx_proj_config)::get(this, "xxx_proj_cfg", xxx_proj_cfg)) begin
		uvm_fatal(get_type_name(), "xxx_proj_cfg not set in config db")
	end
	// So does all the other configurations... test_cfg, dut_cfg, etc.

	//Get from Module UVC config object if not null, otherwise create here 
	if (xxx_proj)cfg.multi_clk_rst_cfg == null) begin
		multi_clk_rst_cfg = multi_clk_rst_config::type_id: create("multi_clk_rst_cfg") ;
		if (!randomize(multi_clk_rst_cfg) begin 
			uvm_fatal(get_type_name(), "Could not randomize config object")
		end
		xxx_proj_cfg.multi_clk_rst_cfg = multi_clk_rst_cfg;
	end	


	if(xxx_proj_cfg.tx_plain_data_if_cfg.size() !== 0) begin
		foreach (tx_plain_data_if_cfg[i]) begin
			tx_plain_data_if_cfg[i] = xxx_proj_cfg.tx_plain_tip_if_cfg[i];
		end 
	end
	foreach(t×_plain_data_if_cfg[i]) begin
		uvm_config_db#(ide_data_config) ::set(this, $sformatf(“tx_plain_data_if[%0d]*"，i)。“ide_data_cfg", t×_plain_data_if_cfg[i]):
	end
	//...
	endfunction