ARM DMIPS算力说明

ARM DMIPS算力说明

ARM算力参考官网地址

https://en.wikipedia.org/wiki/List_of_ARM_processors

Product family	ARM architecture	Processor	Feature	Cache (I / D), MMU	Typical MIPS @ MHz	Reference
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	0.33 DMIPS/MHz
ARM2aS	ARMv2a	ARM250	Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions	None, MEMC1a
		ARM3	First integrated memory cache	4 KB unified	0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit). ARMv3M first added long multiply instructions (32x32=64).	None	10 MIPS @ 12 MHz
		ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)	4 KB unified	28 MIPS @ 33 MHz
		ARM610	As ARM60, cache, no coprocessor bus	4 KB unified	17 MIPS @ 20 MHz 0.65 DMIPS/MHz	[4]
ARM7	ARMv3	ARM700	coprocessor bus (for FPA11 floating-point unit)	8 KB unified	40 MHz
		ARM710	As ARM700, no coprocessor bus	8 KB unified	40 MHz	[5]
		ARM710a	As ARM710, also used as core of ARM7100	8 KB unified	40 MHz 0.68 DMIPS/MHz
ARM7T	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing	None	15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz
		ARM710T	As ARM7TDMI, cache	8 KB unified, MMU	36 MIPS @ 40 MHz
		ARM720T	As ARM7TDMI, cache	8 KB unified, MMU with FCSE (Fast Context Switch Extension)	60 MIPS @ 59.8 MHz
		ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions	None
ARM8	ARMv4	ARM810	5-stage pipeline, static branch prediction, double-bandwidth memory	8 KB unified, MMU	84 MIPS @ 72 MHz 1.16 DMIPS/MHz	[6][7]
ARM9T	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	None
		ARM920T	As ARM9TDMI, cache	16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)	200 MIPS @ 180 MHz	[8]
		ARM922T	As ARM9TDMI, caches	8 KB / 8 KB, MMU
		ARM940T	As ARM9TDMI, caches	4 KB / 4 KB, MPU
ARM9E	ARMv5TE	ARM946E-S	Thumb, enhanced DSP instructions, caches	Variable, tightly coupled memories, MPU
		ARM966E-S	Thumb, enhanced DSP instructions	No cache, TCMs
		ARM968E-S	As ARM966E-S	No cache, TCMs
	ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions	Variable, TCMs, MMU	220 MIPS @ 200 MHz
	ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	No caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)	32 KB / 32 KB, MMU
		ARM1022E	As ARM1020E	16 KB / 16 KB, MMU
	ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)	Variable, MMU or MPU
ARM11	ARMv6	ARM1136J(F)-S	8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access	Variable, MMU	740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz	[9]
	ARMv6T2	ARM1156T2(F)-S	9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions	Variable, MPU		[10]
	ARMv6Z	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	Variable, MMU + TrustZone	965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors	[11]
	ARMv6K	ARM11MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	Variable, MMU
SecurCore	ARMv6-M	SC000	As Cortex-M0		0.9 DMIPS/MHz
	ARMv4T	SC100	As ARM7TDMI
	ARMv7-M	SC300	As Cortex-M3		1.25 DMIPS/MHz
Cortex-M	ARMv6-M	Cortex-M0	Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, no MPU	0.84 DMIPS/MHz	[13]
		Cortex-M0+	Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	0.93 DMIPS/MHz	[14]
		Cortex-M1	Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory	Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU	136 DMIPS @ 170 MHz,[15] (0.8 DMIPS/MHz FPGA-dependent)[16]	[17]
	ARMv7-M	Cortex-M3	Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz	[18]
	ARMv7E-M	Cortex-M4	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz (1.27 w/FPU)	[19]
		Cortex-M7	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions	0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions	2.14 DMIPS/MHz