Exams/2013 q2bfsm

HDLBits的第151练习题：根据描述内容画的状态图如下：

有了状态图，Verilog代码就好写了，如下：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    `define FSM_W 9
    `define FSM_W1 `FSM_W-1
    
    localparam IDLE        =0;
    localparam AFT_RST     =1;
    localparam STRT_X_MNT  =2;
    localparam X1          =3;
    localparam X10         =4;
    localparam X101        =5;
    localparam Y_S0        =6;
    localparam G_O0        =7;
    localparam G_O1        =8;
    
    reg[`FSM_W1:0] state, next_state;
    
    always @(*)begin
        next_state[IDLE] = 1'b0;
        next_state[AFT_RST] = state[IDLE];
        next_state[STRT_X_MNT] = state[AFT_RST]||(x?1'b0:(state[STRT_X_MNT] || state[X10]));
        next_state[X1] = x?state[STRT_X_MNT]||state[X1]:1'b0;
        next_state[X10] = x?1'b0:state[X1];
        next_state[X101] = x?state[X10]:1'b0;
        next_state[Y_S0] = y?1'b0:state[X101];
        next_state[G_O0] = state[G_O0] || (y?1'b0:state[Y_S0]);
        next_state[G_O1] = state[G_O1] || (y?(state[X101] || state[Y_S0]):1'b0);
    end
    
    always @(posedge clk)begin
        if(!resetn)
            state <= `FSM_W'b1;
        else
            state <= next_state;
    end
    
    assign f = state[AFT_RST];
    assign g = (state[X101]||state[Y_S0]||state[G_O1])?1'b1:1'b0;
endmodule