UVM
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Chapter 0 – UVM Guide for Beginners
这是我在学习UVM过程中,查找资料时,无意中从网上看到的一个讲解的例子,例子内容不高深,但对UVM做了很整体的介绍,每个组件的功能以及如何实现,都有简单介绍,感觉对整体了解UVM有很大的帮助。转载 2015-03-30 10:45:17 · 836 阅读 · 0 评论 -
Chapter 6 – Monitor
The monitor is aself-contained model that observes the communication of the DUT with thetestbench. At most, it should observe the outputs of the design and, in case ofnot respecting the protocol’s rul转载 2015-08-04 16:22:15 · 795 阅读 · 0 评论 -
Chapter 10 – Test
At last, we needto create one more block: the test. This block will derive from the uvm_test classand it will have two purposes:Create the env blockConnect the sequencer to the sequenceYou m转载 2015-08-14 09:40:54 · 487 阅读 · 0 评论 -
Chapter 11 – Running the simulation
To run thesimulation, we simply execute the provided Makefile in the GitHub repository:$ make -f Makefile.vcsThe testbenchwill generate random inputs and then those inputs will be sent to the转载 2015-08-14 09:42:43 · 929 阅读 · 0 评论 -
Chapter 8 – Scoreboard
The scoreboardis a crucial element in a self-checking environment, it verifies the properoperation of a design at a functional level. This component is the mostdifficult one to write, it varies from p转载 2015-08-14 09:37:09 · 762 阅读 · 0 评论 -
Chapter 7 – Agent
We have bothmonitors, the sequencer and the driver, so the next step is to connect them up.This is a job for the agent.An agent doesn’trequire a run phase, there is no simulation code to be executed转载 2015-08-14 09:22:27 · 630 阅读 · 0 评论 -
Chapter 4 – Sequences and sequencers
The first step in verifying a RTL design is defining what kind of data should be sent to the DUT. While the driver deals with signal activities at the bit level, it doesn’t make sense to keep this l转载 2015-05-15 10:26:48 · 655 阅读 · 0 评论 -
Chapter 5 – Driver
The driver is a block whose role is tointeract with the DUT. The driver pulls transactions from the sequencer andsends them repetitively to the signal-levelinterface. This interaction will be observ转载 2015-05-15 10:39:01 · 657 阅读 · 0 评论 -
Chapter 3 – Top Block
In a normalproject, the development of the DUT is done separately from the development ofthe testbench, so there are two components that connects both of them:The top block of the testbenchA v转载 2015-04-13 11:01:00 · 919 阅读 · 0 评论 -
Chapter 1 – The DUT
This trainingguide will focus on showing how we can build a basic UVM environment, so thedevice under test was kept very simple in order to emphasize the explanation ofUVM itself.The DUT used isa si转载 2015-04-01 16:27:45 · 673 阅读 · 0 评论 -
Chapter 2 – Defining the verification environment
Beforeunderstanding UVM, we need to understand verification.Right now, wehave a DUT and we will have to interact with it in order to test itsfunctionality, so we need to stimulate it. To achieve thi转载 2015-04-03 15:25:33 · 1094 阅读 · 0 评论