Chapter 0 – UVM Guide for Beginners

这是我在学习UVM过程中，查找资料时，无意中从网上看到的一个讲解的例子，例子内容不高深，但对UVM做了很整体的介绍，每个组件的功能以及如何实现，都有简单介绍，感觉对整体了解UVM有很大的帮助。会把每个章节，陆续的贴上来。

Due to the lack of UVM tutorials for complete beginners, I decided to create a guide that
will assist a novice in building a verification environment using this methodology. I will not
focus on verification techniques nor in the best practices in verifying a digital design, this
guide was thought in helping you to understand the UVM API and in helping you to
successfully compile a complete environment.
The simulator used is Synopsys VCS but the testbench should compile in any HDL
simulator that supports SystemVerilog.

Introduction
As digital systems grow in complexity, verification methodologies get progressively more
essential. While in the early beginnings, digital designs were verified by looking at
waveforms and performing manual checks, the complexity we have today don’t allow for
that kind of verification anymore and, as a result, designers have been trying to find the
best way to automate this process.
The SystemVerilog language came to aid many verification engineers. The language
featured some mechanisms, like classes, covergroups and constraints, that eased some
aspects of verifying a digital design and then, verification methodologies started to
appear.
UVM is one of the methodologies that were created from the need to automate verification.
The Universal Verification Methodology is a collection of API and proven verification
guidelines written for SystemVerilog that help an engineer to create an efficient
verification environment. It’s an open-source standard maintained by Accellera and can
be freely acquired in their website.
By mandating a universal convention in verification techniques, engineers started to
develop generic verification components that were portable from one project to another,
this promoted the cooperation and the sharing of techniques among the user base. It also
encouraged the development of verification components generic enough to be easily
extended and improved without modifying the original code.
All these aspects contributed for a reduced effort in developing new verification
environments, as designers can just reuse testbenches from previous projects and easily
modify the components to their needs.
These series of webpages will provide a training guide for verifying a basic adder block
using UVM. The guide will assume that you have some basic knowledge of SystemVerilog
and will require accompaniment of the following resources:
 Accellera’s UVM User’s Guide 1.1
 Accellera’s UVM 1.1 Class Reference
 Verification Academy’s UVM Cookbook
 Book “SystemVerilog for Verification: A Guide to Learning the TestBench
Language Features“, by Chris Spear
 Book “Comprehensive Functional Verification: The Complete Industry Cycle“, by
John Goss