应用程序获得ARM的cpuid

代码主要是从TCPMP0.72中提取出来，其原理就是操作CP15，当操作CP15的register0且opcode2为0时返回的就是Main ID，opcode2为1是返回的是Cache type。有关CP15的操作是用的汇编代码，而上层调用则是用的C代码，两者结合起来达到应用程序获取cpuid的目的。不过因为TCPMP的代码出来较早，我发现它对cpuid的分析主要是基于"ARM Architecture Reference Manual"、issue为"E"(具体见B2-6)，因为版本较旧所以会有所偏差，对于Context A/M系列前的ARM，如果用"ARMv5 Architecture Reference Manual"、issue为"I"(具体见B3.3)则能够比较准确的分析cpuid及cache信息。
1、汇编代码部分

;***************************************************************************** ;* ;* This program is free software ; you can redistribute it and/or modify ;* it under the terms of the GNU General Public License as published by ;* the Free Software Foundation; either version 2 of the License, or ;* (at your option) any later version. ;* ;* This program is distributed in the hope that it will be useful, ;* but WITHOUT ANY WARRANTY; without even the implied warranty of ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;* GNU General Public License for more details. ;* ;* You should have received a copy of the GNU General Public License ;* along with this program; if not, write to the Free Software ;* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ;* ;* $Id: arm.asm 271 2005-08-09 08:31:35Z picard $ ;* ;* The Core Pocket Media Player ;* Copyright (c) 2004-2005 Gabor Kovacs ;* ;***************************************************************************** AREA |.text|, CODE EXPORT GetCpuId EXPORT GetCPAR EXPORT CPUSpeedClk EXPORT CheckARM5E EXPORT CheckARMXScale EXPORT IRQDisable EXPORT IRQEnable IRQDisable PROC mrs r0, cpsr orr r0, r0, #0x80 msr cpsr_c, r0 mov pc,lr ENDP IRQEnable PROC mrs r0, cpsr bic r0, r0, #0x80 msr cpsr_c, r0 mov pc,lr ENDP CheckARM5E PROC mov r0,#2 qadd r0,r0,r0 qadd r0,r0,r0 qadd r0,r0,r0 qadd r0,r0,r0 cmp r0,#32 moveq r0,#1 movne r0,#0 mov pc,lr CheckARMXScale PROC mov r0,#0x1000000 mov r1,#0x1000000 mar acc0,r0,r1 mov r0,#32 mov r1,#32 mra r0,r1,acc0 cmp r0,#0x1000000 moveq r0,#1 movne r0,#0 cmp r1,#0x1000000 ;64bit or just 40bit? moveq r0,#2 mov pc,lr GetCpuId PROC mrs r0,cpsr and r0,r0,#15 cmp r0,#15 bne UserMode mrc p15,0,r0,c0,c0,0 ;opcode2=0 means "Main ID register" nop nop mrc p15,0,r2,c0,c0,1 ;opcode2=1 means "Cache type register" nop nop str r0,[r1,#0] str r2,[r1,#4] UserMode mov pc,lr ENDP GetCPAR PROC mov r0,#0 mrs r1,cpsr and r1,r1,#15 cmp r1,#15 bne UserMode2 mrc p15,0,r0,c15,c1,0 nop nop UserMode2 mov pc,lr ENDP MACRO speed10 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 add r3,r3,#1 MEND CPUSpeedClk PROC mov r2,r0 mov r1,#3+100 mul r0,r2,r1 ;loop overhead mov r1,#0 CPULoop speed10 speed10 speed10 speed10 speed10 speed10 speed10 speed10 speed10 speed10 subs r2,r2,#1 bgt CPULoop mov pc,lr ENDP END

2、C部分

/***************************************************************************** * * This program is free software ; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * $Id: cpu.c 585 2006-01-16 09:48:55Z picard $ * * The Core Pocket Media Player * Copyright (c) 2004-2005 Gabor Kovacs * ****************************************************************************/ #include <windows.h> #include <Pkfuncs.h> #include "cpu.h" extern int __stdcall CheckARM5E(); extern int __stdcall CheckARMXScale(); extern void __stdcall GetCpuId(int,unsigned long*); void CPUDetect(cpudetect* p); int CPUCaps(); #define CAPS_ARM_5E 0x0001 #define CAPS_ARM_WMMX 0x0002 #define CAPS_ARM_XSCALE 0x1000 #define CAPS_ARM_GENERAL 0x8000 static void SafeGetCpuId(int Id, unsigned long* p) { memset(p,0,4*sizeof(unsigned long)); __try { int Mode = SetKMode(1); GetCpuId(Id,p); SetKMode(Mode); } __except (1) {} } int CPUCaps() { cpudetect p; CPUDetect(&p); return p.Caps; } void CPUDetect(cpudetect* p) { int Caps = 0; unsigned long CpuId[4]; memset(p,0,sizeof(cpudetect)); p->Arch = TEXT("ARM"); SafeGetCpuId(0,CpuId); RETAILMSG(1, (TEXT("0x%08x 0x%08x 0x%08x 0x%08x/r/n"), CpuId[3], CpuId[2], CpuId[1], CpuId[0])); if (CpuId[0]) { p->ICache = 512 << ((CpuId[1] >> 6) & 7); p->DCache = 512 << ((CpuId[1] >> 18) & 7); } else { // when need to detect cpu features somehow // (only works if we can catch cpu exceptions) __try { if (CheckARM5E()) { int XScale; Caps |= CAPS_ARM_5E; XScale = CheckARMXScale(); if (XScale) { p->ICache = p->DCache = 32768; Caps |= CAPS_ARM_XSCALE; if (XScale > 1) Caps |= CAPS_ARM_WMMX; } } } __except (1) {} } if ((CpuId[0] & 0xFF000000) == 0x54000000) //TI { p->Vendor = TEXT("TI"); Caps |= CAPS_ARM_GENERAL; switch ((CpuId[0] >> 4) & 0xFFF) { case 0x915: p->Model = TEXT("915T"); break; case 0x925: p->Model = TEXT("925T"); break; case 0x926: p->Model = TEXT("926T"); Caps |= CAPS_ARM_5E; break; } } else if ((CpuId[0] & 0xFF000000) == 0x41000000) //arm { Caps |= CAPS_ARM_GENERAL; switch ((CpuId[0] >> 4) & 0xFFF) { case 0x920: p->Model = TEXT("920T"); break; case 0x922: p->Model = TEXT("922T"); break; case 0x926: p->Model = TEXT("926E"); Caps |= CAPS_ARM_5E; break; case 0x940: p->Model = TEXT("940T"); break; case 0x946: p->Model = TEXT("946E"); Caps |= CAPS_ARM_5E; break; case 0xA22: p->Model = TEXT("1020E"); Caps |= CAPS_ARM_5E; break; } } else if ((CpuId[0] & 0xFF000000) == 0x69000000) //intel { p->Vendor = TEXT("Intel"); if ((CpuId[0] & 0xFF0000) == 0x050000) //intel arm5e Caps |= CAPS_ARM_5E|CAPS_ARM_XSCALE; if (((CpuId[0] >> 4) & 0xFFF) == 0xB11) { p->Model = TEXT("SA1110"); } else { switch ((CpuId[0] >> 13) & 7) { case 0x2: Caps |= CAPS_ARM_WMMX; break; } switch ((CpuId[0] >> 4) & 31) { case 0x10: p->Model = TEXT("PXA25x/26x"); break; case 0x11: p->Model = TEXT("PXA27x"); break; case 0x12: p->Model = TEXT("PXA210"); break; } } } p->Caps = Caps; }

3、调用实例

typedef struct cpudetect { const wchar_t* Arch; const wchar_t* Vendor; const wchar_t* Model; int Caps; int ICache; int DCache; } cpudetect; cpudetect p; CPUDetect(&p);
4、厂家信息(Main ID的Bits[31:24])
0x41  A (ARM Limited)
0x44  D (Digital Equipment Corporation)
0x4D  M (Motorola - Freescale Semiconductor Inc.)
0x56  V (Marvell Semiconductor Inc.)
0x69  i (Intel Corporation)
5、架构信息(当不是ARM7的时候Main ID的Bits[19:16])
0x1  ARM architecture v4
0x2  ARM architecture v4T
0x3  ARM architecture v5
0x4  ARM architecture v5T
0x5  ARM architecture v5TE
0x6  ARM architecture v5TEJ
0x7  ARM architecture v6
0xF  Revised CPUID format. Details available from ARM.