南京大学数字电路与计算机组成实验的Verilator仿真（一）

南京大学数字电路与计算机组成实验的Verilator仿真

实验一：选择器

1. 2选1多路选择器

top.v

module top(a,b,s,y);
  input   a,b,s;
  output reg  y;   // y在always块中被赋值，一定要声明为reg型的变量

  always @ (*)
    if(s==0)
      y = a;
    else
      y = b;
endmodule

sim_main.cpp

#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Vtop.h"

VerilatedContext* contextp = NULL;
VerilatedVcdC* tfp = NULL;

static Vmux21* top;

void step_and_dump_wave(){
  top->eval();
  contextp->timeInc(1);
  tfp->dump(contextp->time());
}
void sim_init(){
  contextp = new VerilatedContext;
  tfp = new VerilatedVcdC;
  top = new Vmux21;
  contextp->traceEverOn(true);
  top->trace(tfp, 0);
  tfp->open("dump.vcd");
}

void sim_exit(){
  step_and_dump_wave();
  tfp->close();
}

int main() {
  sim_init();

  top->s=0; top->a=0; top->b=0;  step_and_dump_wave();   // 将s，a和b均初始化为“0”
                      top->b=1;  step_and_dump_wave();   // 将b改为“1”，s和a的值不变，继续保持“0”，
            top->a=1; top->b=0;  step_and_dump_wave();   // 将a，b分别改为“1”和“0”，s的值不变，
                      top->b=1;  step_and_dump_wave();   // 将b改为“1”，s和a的值不变，维持10个时间单位
  top->s=1; top->a=0; top->b=0;  step_and_dump_wave();   // 将s，a，b分别变为“1,0,0”，维持10个时间单位
                      top->b=1;  step_and_dump_wave();
            top->a=1; top->b=0;  step_and_dump_wave();
                      top->b=1;  step_and_dump_wave();

  sim_exit();
}

Makefile

#设置变量
ifeq ($(VERILATOR_ROOT),)
VERILATOR = verilator
VERILATOR_COVERAGE = verilator_coverage
else
export VERILATOR_ROOT
VERILATOR = $(VERILATOR_ROOT)/bin/verilator
VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
endif

VERILATOR_FLAGS += -cc --exe
#VERILATOR_FLAGS += -MMD
VERILATOR_FLAGS += -Os -x-assign 0
VERILATOR_FLAGS += -Wall
VERILATOR_FLAGS += --trace
VERILATOR_FLAGS += --assert
VERILATOR_FLAGS += --coverage
VERILATOR_FLAGS += --build
VERILATOR_FLAGS += top.v sim_main.cpp

default:run
run:
	@echo
	@echo "-- Verilator tracing example"
	
	@echo
	@echo "-- VERILATOR-----------------"
	$(VERILATOR)$(VERILATOR_FLAGS)$(VERILATOR_INPUT)
	
	@echo
	@echo"-- RUN-------------------------"
	@rm -rf logs
	@mkdir -p logs
	obj_dir/Vtop +trace

	@echo
	@echo"--DONE---------------------------"
	@echo "To see waveforms,open vlt_dump.vcd in a waveform viewer"
	@echo 

输出结果

2. 2位四选一选择器

top.v

module top(F,Y,X0,X1,X2,X3);
	output reg F;
	input [1:0] Y;
	input X0,X1,X2,X3;
	always@(*)
		case(Y)
			2'b00: F = X0;
			2'b01: F = X1;
			2'b10: F = X2;
			2'b11: F = X3;
			default: F = 1'b00;
		endcase
endmodule

sim_main.cpp

//函数声明部分与上面相同
//下面仅展示int main内部部分
int main(){
	sim_init();
	int i,j;
	top->Y = 00;
	top->X0 = 0;
	top->X1 = 0;
	top->X2 = 0;
	top->X3 = 0; //对各个输入信号初始化
	for(j=0;j<=4;j++){
		for(i=0;i<=16;i++){
			step_and_dump_wave();
			top->X0 = !top->X0;
			if (i%2==1)
				top->X1 = !top->X1;
			if (i%4==3)
				top->X2 = !top->X2;
			if (i%8==7)
				top->X3 = !top->X3;
			printf("Y=%x,X3X2X1X0=%d%d%d%d,F=%x\n",top->Y,top->X3,top->X2,top->X1,top->X0,top->F);
}
	top->Y += 0b01;
	}
	sim_exit();
}

仿真结果