Analog4Fun的博客

原创 Examples of The Fourier Series

典型傅立叶变换事例。

原创 3 Packages Comparison: LFC, CSP and QFN

LFC (Low Profile Fine-pitch Chip Carrier), CSP (Chip Scale Package), and QFN (Quad Flat No-leads) are all types of integrated circuit packaging technologies, each with its own characteristics and applications. Here are the key differences between them:LFC

原创 Slew Rate

linear。

原创 Dependent source model (VCVS, CCCS, CCVS, VCCS)

原创 Review of CMRR

Input CM variations disturb the bias pionts, alternating the small-signal gain and possibly limiting the output voltage swings. More troublesome is the variation of the diff output as a result of a change in Vin,cm, since the circuit is not fully symmetric

原创 Sampling Theorem

Sampling Theorem

原创 Summary of Feedback System

Summary of Feedback System

原创 Chopper Amplifier

chopper amplifier

原创 拉氏变换应用

由系统函数零、极点分别决定时域特性（一）零、极点分布与波形特征的对应的零、极点：典型情况极点分布与原函数波形对应关系极点位于s平面坐标原点，冲激响应为阶跃函数 极点位于s平面实轴上，冲激响应具有指数形式，正为指数增长，负为指数衰减 虚轴上共轭极点给出等幅振荡 极点落在s平面左平面内共轭极点对应衰减震荡（左平面衰减，共轭极点振荡）多重极点典型情况（一般几重极点就乘上t的几次方）位于s平面坐标原点的二阶或三阶极点分别给出时间函数为t或他(1/2)t^2 实轴上二阶极点给出t与指数函数的

原创 PSS and PNoise

1. PSS: periodic steady-stateUsing Harmonic balance (in the frequency domain): 1)simulating weak non-linear circuits; 2) handling frequency dependent componentsor shooting (in the time domain): highly non-linear circuits with sharply rising and falling

原创 Jitter

1. Period Jitterfile:///Users/ssong/Downloads/AN10007-Jitter-and-measurement%20(3).pdf1.1 Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles.Period jitter is...

原创 Convolution

概率论中，两个统计独立变量X与Y的和的概率密度函数(PDF) 是X与Y的概率密度函数的卷积。如何通俗易懂地解释卷积？ - 知乎卷积，这个堪称神解释 - 知乎

原创 Power consumption (Low power design)

https://www.eurasip.org/Seminars/EURASIPLowPowerSeminar_talk1.pdf

原创 Dennard scaling

Dennard提出，晶体管的尺寸在每一代技术中都缩小了30% (0.7倍)，因此它们的面积A减少了50%。这意味着电路减少了30% (0.7倍)的延迟，因此增加了约40% (1.4倍)的工作频率。最后，为了保持电场恒定，电压降低了30%，能量降低了65%，功率降低了50%。因此，在每一代技术中，晶体管密度增加一倍，电路速度提高40%，功耗(晶体管数量增加一倍)保持不变(https://www.ithome.com/0/451/930.htm)。1 Dennard et al. Design of...

原创 Resistor Tempco

TSMCPpoly (Neg tempco)typ: 39.96K ohm-40C: 41.04K ohm, +2.7%125C: 38.84K ohm, -2.8%Rmetal (Pos tempco)typ: 5 ohm-40C: 4.192 ohm, -16.16%125C: 6.222 ohm, +24.44%

原创 Latch-up

Latch up 最易产生在易受外部干扰的I/O电路处, 也偶尔发生在内部电路。1. 原理Latch up 是指cmos晶片中, 在电源power VDD和地线GND(VSS)之间由于寄生的PNP和NPN双极性BJT相互影响而产生的一低阻抗通路, 它的存在会使VDD和GND之间产生大电流。Latch-up发生的条件：(i)当两个BJT都导通，在VDD和GND之间产生低阻抗通路;(ii) 两个晶体管反馈回路（feedback loop）增益的乘积大于1;PNP为一垂直式PNP

原创 RHP-Zero

https://www.powerelectronics.com/technologies/power-management/article/21860287/understanding-the-righthalfplane-zero-part-1任何升压类变换器，工作于连续导电模式都会存在右半平面零点。减弱和消除右半平面零点的方式有很多，最简单的方式就是工作于DCM模式。Boost变换器，右半平面零点直接体现为：负载发生变化时，占空比不会立即向稳态值靠近，因此瞬态响应性能较差，也导致了补偿网络较难

原创 Pole location vs. Tran behavior

https://web.mit.edu/2.14/www/Handouts/PoleZero.pdfThe location of the poles in the s-plane therefore define the n components in the homogeneous response as described below:1. A real pole pi = −σ in the left-half of the s-plane defines an exponentially