主要加了写CLCOK和reset信号
module adder_signed_fixed_point_32bit_with_overflow (
input CLOCK,RESET,
input iCall,
output oDone,
input signed [31:0] a,
input signed [31:0] b,
output signed [31:0] sum,
output reg overflow
);
reg isDone;
assign sum = a + b;
always @ ( posedge CLOCK or negedge RESET )
if( !RESET )
begin
overflow <= 1'b0;
isDone <= 1'b0;
end
else if( iCall )
begin
if ((a > 0 && b > 0 && sum < 0) ||
(a < 0 && b < 0 && sum > 0))
begin
overflow = 1;
end else begin
overflow = 0;
end
isDone <= 1'b1;
end
assign oDone = isDone;
endmodule