APP_UART_FIFO_INIT()
↓
app_uart_init()
↓
uart_event_handler()
↓
nrf_drv_uart_tx()
↓
nrfx_uarte_tx()
↓
nrf_uarte_tx_buffer_set()
↓
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
}
NRF_UARTE_Type:结构体定义
typedef struct { /*!< UARTE Structure */
__O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
__O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
__O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
__O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
__I uint32_t RESERVED0[7];
__O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */
__I uint32_t RESERVED1[52];
__IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
__IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
__IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to
Data RAM) */
__I uint32_t RESERVED2;
__IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */
__I uint32_t RESERVED3[2];
__IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
__IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */
__IO uint32_t EVENTS_ERROR; /*!< Error detected */
__I uint32_t RESERVED4[7];
__IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
__I uint32_t RESERVED5;
__IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */
__IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */
__I uint32_t RESERVED6;
__IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */
__I uint32_t RESERVED7[41];
__IO uint32_t SHORTS; /*!< Shortcut register */
__I uint32_t RESERVED8[63];
__IO uint32_t INTEN; /*!< Enable or disable interrupt */
__IO uint32_t INTENSET; /*!< Enable interrupt */
__IO uint32_t INTENCLR; /*!< Disable interrupt */
__I uint32_t RESERVED9[93];
__IO uint32_t ERRORSRC; /*!< Error source */
__I uint32_t RESERVED10[31];
__IO uint32_t ENABLE; /*!< Enable UART */
__I uint32_t RESERVED11;
UARTE_PSEL_Type PSEL; /*!< Unspecified */
__I uint32_t RESERVED12[3];
__IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */
__I uint32_t RESERVED13[3];
UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */
__I uint32_t RESERVED14;
UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */
__I uint32_t RESERVED15[7];
__IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
} NRF_UARTE_Type;