FPGA与DSP5509A通过MCBSP接口通信

最新推荐文章于 2021-06-14 15:51:45 发布

王纯配

最新推荐文章于 2021-06-14 15:51:45 发布

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分类专栏： FPGA 文章标签： MCBSP 5509 fpga

本文链接：https://blog.csdn.net/aqwtyyh/article/details/77995508

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DSP5509A：

#include <stdio.h>
#include <csl_mcbsp.h>

MCBSP_Handle rMcbsp,tMcbsp;

MCBSP_Config Mcbsp0Config = {
	MCBSP_SPCR1_DEFAULT,
	MCBSP_SPCR2_DEFAULT,
	/*单数据相，接受数据长度为16位,每相1个数据*/
    MCBSP_RCR1_RMK( 
    	MCBSP_RCR1_RFRLEN1_OF(0),              /* RFRLEN1 = 0 */
  		MCBSP_RCR1_RWDLEN1_16BIT                /* RWDLEN1 = 0 */
    ),
    MCBSP_RCR2_RMK(    
		MCBSP_RCR2_RPHASE_SINGLE,              /* RPHASE  = 0 */
		MCBSP_RCR2_RFRLEN2_OF(0),              /* RFRLEN2 = 0 */
		MCBSP_RCR2_RWDLEN2_8BIT,               /* RWDLEN2 = 0 */
		MCBSP_RCR2_RCOMPAND_MSB,               /* RCOMPAND = 0 */
		MCBSP_RCR2_RFIG_YES,                   /* RFIG    = 0 */
		MCBSP_RCR2_RDATDLY_1BIT                /* RDATDLY = 1 接收数据1位延时不用改*/
    ),  
    MCBSP_XCR1_DEFAULT,
    MCBSP_XCR2_DEFAULT,
  	MCBSP_SRGR1_DEFAULT,
 	MCBSP_SRGR2_DEFAULT,  
    MCBSP_MCR1_DEFAULT,
 	MCBSP_MCR2_DEFAULT,
 	MCBSP_PCR_DEFAULT,
    MCBSP_RCERA_DEFAULT, 
	MCBSP_RCERB_DEFAULT, 
	MCBSP_RCERC_DEFAULT, 
	MCBSP_RCERD_DEFAULT, 
	MCBSP_RCERE_DEFAULT, 
	MCBSP_RCERF_DEFAULT, 
	MCBSP_RCERG_DEFAULT, 
	MCBSP_RCERH_DEFAULT, 
	MCBSP_XCERA_DEFAULT,
	MCBSP_XCERB_DEFAULT,
	MCBSP_XCERC_DEFAULT,
	MCBSP_XCERD_DEFAULT,  
	MCBSP_XCERE_DEFAULT,
	MCBSP_XCERF_DEFAULT,  
	MCBSP_XCERG_DEFAULT,
	MCBSP_XCERH_DEFAULT
};

MCBSP_Config Mcbsp1Config = {
	MCBSP_SPCR1_DEFAULT,
	MCBSP_SPCR2_DEFAULT,
	MCBSP_RCR1_DEFAULT,
	MCBSP_RCR2_DEFAULT,
	/*单数据相，发送数据长度为16位,每相1个数据*/
    MCBSP_XCR1_RMK(    
	    MCBSP_XCR1_XFRLEN1_OF(0),              /* XFRLEN1 = 0 */ 
	    MCBSP_XCR1_XWDLEN1_16BIT                /* XWDLEN1 = 0 */   
	),   
 	MCBSP_XCR2_RMK(   
	    MCBSP_XCR2_XPHASE_SINGLE,              /* XPHASE  = 0 */
	    MCBSP_XCR2_XFRLEN2_OF(0),              /* XFRLEN2 = 0 */
	    MCBSP_XCR2_XWDLEN2_8BIT,               /* XWDLEN2 = 0 */
	    MCBSP_XCR2_XCOMPAND_MSB,               /* XCOMPAND = 0 */
	    MCBSP_XCR2_XFIG_YES,                   /* XFIG    = 0 */
	    MCBSP_XCR2_XDATDLY_1BIT                /* XDATDLY = 1 发送数据也是1位延时*/
	),
  	MCBSP_SRGR1_DEFAULT,
 	MCBSP_SRGR2_DEFAULT,  
    MCBSP_MCR1_DEFAULT,
 	MCBSP_MCR2_DEFAULT,
 	MCBSP_PCR_DEFAULT,
    MCBSP_RCERA_DEFAULT, 
	MCBSP_RCERB_DEFAULT, 
	MCBSP_RCERC_DEFAULT, 
	MCBSP_RCERD_DEFAULT, 
	MCBSP_RCERE_DEFAULT, 
	MCBSP_RCERF_DEFAULT, 
	MCBSP_RCERG_DEFAULT, 
	MCBSP_RCERH_DEFAULT, 
	MCBSP_XCERA_DEFAULT,
	MCBSP_XCERB_DEFAULT,
	MCBSP_XCERC_DEFAULT,
	MCBSP_XCERD_DEFAULT,  
	MCBSP_XCERE_DEFAULT,
	MCBSP_XCERF_DEFAULT,  
	MCBSP_XCERG_DEFAULT,
	MCBSP_XCERH_DEFAULT
};

void main(void)
{
	Uint16 leddata;
	
	CSL_init();		//初始化CSL库
	/*DSP接收数据使用MCBSP0,发送数据使用MCBSP1*/
	rMcbsp = MCBSP_open(MCBSP_PORT0,MCBSP_OPEN_RESET);//初始化McBSP0
	MCBSP_config(rMcbsp,&Mcbsp0Config);//设置McBSP0
	MCBSP_start(rMcbsp,MCBSP_RCV_START,0);//启动McBSP0
	
	tMcbsp = MCBSP_open(MCBSP_PORT1,MCBSP_OPEN_RESET);//初始化McBSP1
	MCBSP_config(tMcbsp,&Mcbsp1Config);//设置McBSP1
	MCBSP_start(tMcbsp,MCBSP_XMIT_START,0);//启动McBSP1
	
	while(1)
	{
		while(!MCBSP_rrdy(rMcbsp)){};
		leddata = MCBSP_read16(rMcbsp);
		printf("%d\n",leddata);
		leddata=leddata+1;	
		while(!MCBSP_xrdy(tMcbsp)){};
		MCBSP_write16(tMcbsp,leddata);			
	}; 
	
}

FPGA部分：

module McBSP(CLK,RESET,DR,DX,CLKR,CLKX,FSX,FSR,DATA,CLKG);
/*CLKG为signaltap抓取时钟，DATA为被抓取对象，两个信号仅作观测，未使用*/
input CLK,DX,RESET;
output CLKR,CLKX,FSR,FSX,DR,DATA,CLKG;

parameter T100MS=15'd25_000;   /*100ms定时产生帧同步信号*/
reg CLKR,CLKX,FSR,FSX,DR,CLKG;
//fpga发送端定义
reg [15:0]num[499:0];
reg [15:0]buff;
reg [3:0]flag;
reg [14:0]Count1;
reg [15:0]i;
reg [3:0]k;
//fpga接收端定义
reg [15:0]buff2;
reg [4:0]flag2;
reg [14:0]Count2;
reg [3:0]j;
reg [15:0]DATA;
reg [5:0]count;
/*500个数据初始化*/
initial
begin
for(i=0;i<500;i=i+1)
	num[i]=i;	
end
/*设置时钟频率为512K*/
always@(posedge CLK or negedge RESET)
	if(!RESET)
	begin
		CLKR<=1'b1;
		CLKX<=1'b0;
		count<=6'd0;
	end
	else if(count==50)
	begin		
		CLKR<=~CLKR;
		CLKX<=~CLKX;
		count<=6'd1;
	end
	else 
	count<=count+1;
/*DSP设置为CLKR时钟下降沿读取数据，FPGA在上升沿向dsp发送数据，帧同步信号在下降沿发送*/
always@(negedge CLKR or negedge RESET)
begin
	if(!RESET)
	begin
		FSR<=1'b0;
		Count1<=15'd0;
		i<=16'd0;
	end
	else if(Count1==T100MS)
	begin
	   Count1<=15'd1;	
		FSR<=1'b1;
		buff<=num[i];
		if(i<499)
		i<=i+1;
		else
		i<=16'd0;
	end
	else if(FSR)
	begin
		FSR<=1'b0;
		Count1<=Count1+1;	
	end
	else
	   Count1<=Count1+1;
	
end

always@(posedge CLKR or negedge RESET)
begin
	if(!RESET)
	begin
		flag<=4'd0;
		k<=4'd15;
	end
	else if(FSR)
	begin
		flag<=4'd15;
		DR<=buff[k];
		k<=k-1;
	end
	else if(flag)
	begin	
		flag<=flag-1;
		DR<=buff[k];	
		if(k)
			k<=k-1;
		else
			k<=4'd15;
	end
end
/*DSP设置为CLKX时钟上升沿发送数据，FPGA在下降读取dsp发送的数据，帧同步信号在上升沿发送*/
always@(posedge CLKX or negedge RESET)
begin
	if(!RESET)
	begin
		FSX<=1'b0;
		Count2<=15'd0;
	end
	else if(Count2==T100MS)
	begin
	   Count2<=15'd1;
		FSX<=1'b1;
	end
	else if(FSX)
	begin
		FSX<=1'b0;
		Count2<=Count2+1;
	end
	else
	   Count2<=Count2+1;
end

always@(negedge CLKX or negedge RESET)
begin	
	if(!RESET)
	begin
		flag2<=5'd0;
		buff2<=16'h0;
		CLKG<=1'b0;
	end
	else if(FSX)
	begin
		flag2<=5'd16;
		DATA<=buff2;
		j<=4'd15;
		CLKG<=1'b1;
	end
	else if(flag2)
	begin
		flag2<=flag2-1;
		buff2[j]<=DX;
		if(j==0)
			CLKG<=1'b0;
		else
			j<=j-1;
	end
end

endmodule