2021-05-07

1.4位加法器的门级建模代码

module fulladd(S,Cout,Cin,A,B);

output S,Cout;

input Cin,A,B;

wire and1,and2,and3,and4;

xor (S,Cin,A,B);

and (and1,Cin,A);

and (and2,A,B);

and (and3,Cin,B);

or (Cout,and1,and2,and3);

endmodule

 

module add4a(S3,S2,S1,S0,COUT,CIN,X3,X2,X1,X0,Y3,Y2,Y1,Y0);

output COUT,S3,S2,S1,S0;

input CIN, X3,X2,X1,X0,Y3,Y2,Y1,Y0;

wire c0,c1,c2;

fulladd add0(.S(S0), .Cout(c0), .Cin(CIN), .A(X0), .B(Y0));

fulladd add1(.S(S1), .Cout(c1), .Cin(c0), .A(X1), .B(Y1));

fulladd add2(.S(S2), .Cout(c2), .Cin(c1), .A(X2), .B(Y2));

fulladd add3(.S(S3), .Cout(COUT), .Cin(c2), .A(X3), .B(Y3));

endmodule

module add4(S,COUT,CIN,X,Y);//ËÄλȫ¼ÓÆ÷

output COUT;

output [3:0] S;

input CIN;

input [3:0]X,Y;

wire c0,c1,c2;

fulladd add0(.S(S[0]), .Cout(c0), .Cin(CIN), .A(X[0]), .B(Y[0]));

fulladd add1(.S(S[1]), .Cout(c1), .Cin(c0), .A(X[1]), .B(Y[1]));

fulladd add2(.S(S[2]), .Cout(c2), .Cin(c1), .A(X[2]), .B(Y[2]));

fulladd add3(.S(S[3]), .Cout(COUT), .Cin(c2), .A(X[3]), .B(Y[3]));

endmodule

module tadd4;

reg [3:0] x,y;

reg cin;

wire [3:0] s;

wire cout;

add4 myadd4(.S(s),.COUT(cout),.CIN(cin),.X(x),.Y(y));

initial

begin

cin<=0;x<=11;y<=2;

#10 cin<=0;x<=9;y<=6;

#10 cin<=0;x<=9;y<=7;

#10 cin<=1;x<=11;y<=2;

#10 cin<=1;x<=9;y<=6;

#10 cin<=1;x<=9;y<=7;

#10 $stop;

end

endmodule

module fulladd(sum,c_out,a,b,c_in);

output sum,c_out;

input a,b,c_in;

wire s1,c1,c2;

xor (s1,a,b);

and (c1,a,b);

xor (sum,s1,c_in);

and (c2,s1,c_in);

or (c_out,c2,c1);

endmodule

2.verilog Modlsim仿真代码

2.test

 

module test;

wire sum,c_out;

reg a,b,c_in;

fulladd fadd(sum,c_out,a,b,c_in);

/*

initial

begin

#15 force fadd.sum=a&b&c_in;

#20 release fadd.sum;

 

#10 $stop;

end

*/

initial

begin

a=0;b=0;c_in=0;

#10 a=0;b=0;c_in=1;

#10 a=0;b=1;c_in=0;

#10 a=0;b=1;c_in=1;

#10 a=1;b=0;c_in=0;

#10 a=1;b=0;c_in=1;

#10 a=1;b=1;c_in=0;

#10 a=1;b=1;c_in=1;

#10 $stop;

end

endmodule

3.视频链接

https://b23.tv/FYsAfg