16位数据转128位数据

输入数据：data_in[15:0]   valid_in

输出数据：data_out[127:0]  valid_out

思维逻辑很简单，看仿真。valid_out计数到7的时候拉高一次即可。

---

module data_16_128(
input                  clk,
input                  rst_n,
input                  valid_in,
input        [15:0]    data_in,

output                valid_out,
output   [127:0]       data_out
);

reg   [3:0]    data_cnt;
reg   [127:0]  data_out_r;
reg   [0:0]    valid_out_r ;


assign  data_out=data_out_r;
assign  valid_out=valid_out_r;
         
always@(posedge   clk or negedge  rst_n)
      begin  
        if(!rst_n)
          begin
             valid_out_r <=1'd0;
             data_out_r<=128'd0;
             data_cnt   <=4'd0;
         end
     else
        if(valid_in)
          begin
             
             data_cnt<=(data_cnt<7?data_cnt+1:0);
             data_out_r<={data_in[15:0], data_out_r[127:16]};
                if(data_cnt==4'd7)
                    valid_out_r<=1'b1;
                else
                    valid_out_r<=1'b0;                   
           end
      end 

endmodule

仿真代码输入数据产生随机数据对比数据转换是否正确。

module testbench();

reg            clk;
reg            rst_n;
reg  [15:0]    data_in;
reg            valid_in;

wire           valid_out;
wire [127:0]    data_out;

initial
    begin
       clk=1'b0;
       rst_n=1'b0;
    #20
       rst_n=1'b1;

   repeat(13)begin      
       #20
         valid_in<=1;
       #1000
         valid_in<=0;
     end
   $stop;
 end

always #10  clk=!clk;


       
integer seed;



initial  
  begin 
   seed = 0;
   end

always @(posedge clk) 
  begin data_in <= $random(seed);
 end


data_16_128 data_16_128_inst(
.clk      (clk      ),
.rst_n    (rst_n    ),
.data_in  (data_in  ),
.valid_in (valid_in ),        
.data_out (data_out ),
.valid_out(valid_out)
);


endmodule

仿真结果如下：