flash的dma操作
nand_init()
{
//Flash_IO_dma_control 数据FIFO DMA使能和控制信息
//将memory target设置为NAND Flash,就是主内存和nand flash之间进行DMA数据传输
writel(FIO_DMACTR_REG,(readl(FIO_DMACTR_REG) & 0xcfffffff);
//Force ReadID with 4-cycles
writel(NAND_CTR_REG,readl(NAND_CTR_REG)|NAND_CTR_I4);
//Reset chip 这个函数实现及过程在下面给出
nand_wait_cmd_done(NAND_CMD_RESET);
//Read ID
nand_wait_cmd_done(NAND_CMD_READID);
id = readl(NAND_ID_REG);
}
void nand_wait_cmd_done(u32 cmd)
{
/*NAND_CMD_REG命令寄存器的后4位为命令标示位,具体命令详见芯片手册*/
writel(NAND_CMD_REG,cmd);
rct_timer2_reset_count();
while(1)
{
/*读命令完成中断状态寄存器,命令完成后该中断标志会自动置为1*/
if(readl(NAND_INT_REG) & NAND_INT_DI)// 0x1
{
break;
}
if(rct_timer2_get_count() >= NAND_CMD_TIMEOUT)
{
putstr("nand cmd timeout:");
puthex(cmd);
putstr("\r\n");
while(1);
}
}
/*将中断完成标志为重新置为0*/
writel(NAND_INT_REG,0x0);
}
nand_reset()
{
/*Reset FIO FIFO,and Exit random read mode*/
setbitsl(FIO_CTR_REG,FIO_CTR_RR);
rct_timer2_dly_ms(1);/*delay is must have*/
clrbitsl(FIO_CTR_REG,FIO_CTR_RR);
/*Clear the FIO DMA Status Register*/
writel(FIO_DMASTA_REG,0x0);
/*Setup FIO DMA Control Register*/
/*FIO_DMACTR_TS4B Transfer size 在AHB总线上每次传输的数据大小4字节*/
writel(FIO_DMACTR_REG,FIO_DMACTR_FL | FIO_DMACTR_TS4B);
/*Setup NAND Flash Control Register*/
/*参考下面nand_control寄存器指定的相应位*/
writel(NAND_CTR_REG,flnand.control);
/*清中断状态位*/
writel(NAND_INT_REG,0x0);
/*Setup flash timing register*/
/*关于时序这块可参考下面详细的介绍*/
writel(NAND_TIM0_REG,flnand.timing0);
........
return 0;
}
//这些时序在nandflash的datasheet中可以查得
#define NAND_