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最新推荐文章于 2022-04-28 21:11:58 发布

banshan6542

最新推荐文章于 2022-04-28 21:11:58 发布

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原文链接：http://www.cnblogs.com/HoseaTec/p/8722062.html

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 Verilog/VHDL
 Synthesis (even just for FPGA)
 Static Timing (setup time/hold time)
 Back-annotated gate level simulation
 Basic digital design concepts (FSM, data pipelines, etc.)
 Basic UNIX skills, emacs/vim, grep, find, man
 Basic programming (C, C++, perl, shell scripting)

 BS degree

 I expect more from an MS (at least some of the following):
 Verification methodology
 Vera/SystemVerilog/SystemC
 Assertions
 Functional Coverage
 Fault Coverage (scan, custom patterns)
 Power considerations
 Clock domain crossings
 Deep sub-micron Static timing considerations (OCV)
 Understanding of basic common architectures (SPI, UART, I2C,
 microprocessors (x86/arm/arc/powerpc)
 Standard cell library construction
 Clock tree design
 Reset synchronization
 Clock gating
 Basic resources (DDR DRAM, SRAM, PLL, DLL, etc.)
 Fifo design
 Clock divider design

转载于:https://www.cnblogs.com/HoseaTec/p/8722062.html