同步UART计数器不起作用！求助！

最新推荐文章于 2024-08-14 17:02:31 发布

black_rx_king

最新推荐文章于 2024-08-14 17:02:31 发布

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文章标签： fpga开发

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跟着B站上的视频做的，但是跑出来的波形图输出没反应

`timescale 1ns / 1ps
module uart_rxd(
    input uart_clk,//153.6khz
    input sys_rst,
    input rxd,
    output reg[7:0]rx_data,
    output reg rx_flag
    );
    reg [7:0]cnt;
    parameter s0=1'd0,s1=1'd1;
    reg state;
    `define  ep  8'd161
    //节拍计数
    always@(posedge uart_clk,negedge sys_rst)begin
        if(!sys_rst)begin
            cnt <= 8'd0;
            state <= s0;
        end
       else begin
            case(state)
                s0:begin
                    if(rxd == 1'd0)begin
                        state <= s1;
                    end
                    else 
                        state <= s0;
                end
                s1:begin
                    if(cnt < `ep)begin
                        cnt <= cnt+1'd1;
                    end
                    else    begin
                        cnt <= 8'd0;
                        state <= s0;
                    end
                end
                default:state <= s0;
            endcase
       end
    end
    //根据节拍，做出相应行为
    always@(posedge uart_clk , negedge sys_rst)begin
        if(!sys_rst)begin
            rx_data <= 8'd0;
            rx_flag <= 1'd0;
        end
        else begin
            case(cnt)
                7+1*16:rx_data[0] <= rxd;
                7+2*16:rx_data[1] <= rxd;
                7+3*16:rx_data[2] <= rxd; 
                7+4*16:rx_data[3] <= rxd; 
                7+5*16:rx_data[4] <= rxd; 
                7+6*16:rx_data[5] <= rxd; 
                7+7*16:rx_data[6] <= rxd; 
                7+8*16:rx_data[7] <= rxd;   
                10*16:rx_flag <= 1'd1;
                10*16+1:rx_flag <= 1'd0;
                default:;
            endcase
        end
    end
    
endmodule

`timescale 1ns / 1ps
module uart_rxd_tb();
`define bps 9600
`define tbps (1000_000_000/`bps)
`define uartclk 9600*`bps
`define tuartclk (1000_000_000/`uartclk)
`define half_clk (`tuartclk/2)

reg [7:0]temp_data;
    reg uart_clk;
    reg sys_rst;
    reg rxd;
    wire [7:0]rx_data;
    wire rx_flag;
uart_rxd uart_rxd_list(
    .uart_clk(uart_clk),
    .sys_rst(sys_rst),
    .rxd(rxd),
    .rx_data(rx_data),
    .rx_flag(rx_flag)
);
initial uart_clk=1'd1;
always #`half_clk uart_clk = ~uart_clk;
initial begin
    sys_rst = 1'd0;
    rxd = 1'd1;
    temp_data = 8'd0;
    #200.1
    sys_rst = 1'd1;
    #10000
    rxd = 1'd0;
    temp_data = 8'd55;
    #`tbps
    rxd = temp_data[0];
    #`tbps
    rxd = temp_data[1];
    #`tbps
    rxd = temp_data[2];
    #`tbps
    rxd = temp_data[3];
    #`tbps
    rxd = temp_data[4];
    #`tbps
    rxd = temp_data[5];
    #`tbps
    rxd = temp_data[6];
    #`tbps
    rxd = temp_data[7];
    #`tbps
    rxd = 1'd1;
end
endmodule