chipyard环境下仿真risc-v教程（1）：运行chipyard中的默认案例

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最新推荐文章于 2024-08-10 08:03:03 发布

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分类专栏： RISC-V

原文链接：https://chipyard.readthedocs.io/en/latest/Simulation/Software-RTL-Simulation.html#sw-rtl-sim-intro

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该教程介绍了如何在Chipyard框架下安装必要的工具链，编译默认示例，运行单个和一组测试案例，并展示了verilator中make命令的用法。通过这些步骤，读者可以学习到Chipyard的基本操作和RISC-V处理器的测试流程。

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官网教程：链接

chipyard太难了，我暂时不继续写这个教程了，先弄懂简单的risc工程再来看chipyard…

步骤

（1）按照官网教程安装好chipyard

chipyard中已经包含了所需的toolchain和verilator，不用自己再去下载一遍，chipyard网上教程还是蛮多的，官网也有教程，这里暂时不放了。

（2）进入verilator目录

cd chipyard/sims/verilator

（3）编译chipyard中的default example

make

一段时间后，会生成一个叫simulator-chipyard-RocketConfig的文件，接下来可以利用这个文件来运行我们想测试的example。

一定要make！不然后面的步骤无法继续。（output是后续生成的，可以先不管。）
在这里插入图片描述

（4）测试单个例子

./simulator-chipyard-RocketConfig命令后面接上名字是xxx的（risc生成的）二进制文件，就可以运行了。

./simulator-chipyard-RocketConfig xxx

比如，官网给出了下面这个例子：

./simulator-chipyard-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

为了简便，chipyard官方说也可以用make run-binary BINARY=xxx 代替 ./simulator-chipyard-RocketConfig xxx

make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

在这里插入图片描述

（5）将一组测试案例进行测试

chipyard提供了如下两个命令，可以对同时测试案例库中的一组案例。
下面的命令还是在chipyard/sims/verilator目录下执行的。

make run-asm-tests
make run-bmark-tests

运行完成后，在output文件夹下会生成相应结果。
在这里插入图片描述

（5）查看verilator中make还有哪些用法

chipyard/sims/verilator$ make help

输出为：

design specifier variables:
 ---------------------------
   SUB_PROJECT            = use the specific subproject default variables [chipyard]
   SBT_PROJECT            = the SBT project that you should find the classes/packages in [chipyard]
   MODEL                  = the top level module of the project in Chisel (normally the harness) [TestHarness]
   VLOG_MODEL             = the top level module of the project in Firrtl/Verilog (normally the harness) [TestHarness]
   MODEL_PACKAGE          = the scala package to find the MODEL in [chipyard]
   CONFIG                 = the configuration class to give the parameters for the project [RocketConfig]
   CONFIG_PACKAGE         = the scala package to find the CONFIG class [chipyard]
   GENERATOR_PACKAGE      = the scala package to find the Generator class in [chipyard]
   TB                     = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [TestDriver]
   TOP                    = top level module of the project (normally the module instantiated by the harness) [ChipTop]

 compilation variables:
 ----------------------
   EXTRA_GENERATOR_REQS   = additional make requirements needed for the main generator
   EXTRA_SIM_CXXFLAGS     = additional CXXFLAGS for building simulators
   EXTRA_SIM_LDFLAGS      = additional LDFLAGS for building simulators
   EXTRA_SIM_SOURCES      = additional simulation sources needed for simulator
   EXTRA_SIM_REQS         = additional make requirements to build the simulator
   ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client
   VERILATOR_PROFILE      = 'none' if no verilator profiling (default)
                            'all' if full verilator runtime profiling
                            'threads' if runtime thread profiling only
   VERILATOR_THREADS      = how many threads the simulator will use (default 1)
   VERILATOR_FST_MODE     = enable FST waveform instead of VCD. use with debug build

 simulation variables:
 ---------------------
   BINARY                 = riscv elf binary that the simulator will run when using the run-binary* targets
   VERBOSE_FLAGS          = flags used when doing verbose simulation [+verbose]
   EXTRA_SIM_FLAGS        = additional runtime simulation flags (passed within +permissive)
   NUMACTL                = set to '1' to wrap simulator in the appropriate numactl command

 some useful general commands:
 -----------------------------
   help                   = display this help
   default                = compiles non-debug simulator [./simulator-chipyard-RocketConfig]
   debug                  = compiles debug simulator [./simulator-chipyard-RocketConfig-debug]
   clean                  = remove all debug/non-debug simulators and intermediate files
   clean-sim              = removes non-debug simulator and simulator-generated files
   clean-sim-debug        = removes debug simulator and simulator-generated files
   run-binary             = run [./simulator-chipyard-RocketConfig] and log instructions to file
   run-binary-fast        = run [./simulator-chipyard-RocketConfig] and don't log instructions
   run-binary-debug       = run [./simulator-chipyard-RocketConfig-debug] and log instructions and waveform to files
   verilog                = generate intermediate verilog files from chisel elaboration and firrtl passes
   firrtl                 = generate intermediate firrtl files from chisel elaboration
   run-tests              = run all assembly and benchmark tests
   launch-sbt             = start sbt terminal