1. 中断向量表
当一个异常或者中断发生时,处理器会把pc设置为一个特定的存储器地址。这一地址放在一个被称为向量(vector table)的特定的地址范围内。
2. vector_irq
2.1 vector_stub宏
vector_stub宏定义如下:
1027 .macro vector_stub, name, mode, correction=0
1028 .align 5
1029
1030 vector_\name:
1031 .if \correction
1032 sub lr, lr, #\correction
1033 .endif
1034
1035 @
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1037 @ (parent CPSR)
1038 @
1039 stmia sp, {r0, lr} @ save r0, lr
1040 mrs lr, spsr
1041 str lr, [sp, #8] @ save spsr
1042
1043 @
1044 @ Prepare for SVC32 mode. IRQs remain disabled.
1045 @
1046 mrs r0, cpsr
1047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1048 msr spsr_cxsf, r0
1049
1050 @
1051 @ the branch table must immediately follow this code
1052 @
1053 and lr, lr, #0x0f
1054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 mov r0, sp
1057 ARM( ldr lr, [pc, lr, lsl #2] )
1058 movs pc, lr @ branch to handler in SVC mode
1059 ENDPROC(vector_\name)
2.2 vector_irq
1077 /*
1078 * Interrupt dispatcher
1079 */
1080 vector_stub irq, IRQ_MODE, 4
1081
1082 .long __irq_usr @ 0 (USR_26 / USR_32)
1083 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1084 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1085 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1086 .long __irq_invalid @ 4
1087 .long __irq_invalid @ 5
1088 .long __irq_invalid @ 6
1089 .long __irq_invalid @ 7
1090 .long __irq_invalid @ 8
1091 .long __irq_invalid @ 9
1092 .long __irq_invalid @ a
1093 .long __irq_invalid @ b
1094 .long __irq_invalid @ c
1095 .long __irq_invalid @ d
1096 .long __irq_invalid @ e
1097 .long __irq_invalid @ f
1098
1099 /*
vector_irq的定义包含两部分: 1080展开的部分和1082-1097行的部分。
展开的vector_irq的定义如下:
1030 vector_irq:
1031 .if \correction
1032 sub lr, lr, #\correction
1033 .endif
1034
1035 @
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1037 @ (parent CPSR)
1038 @
1039 stmia sp, {r0, lr} @ save r0, lr
1040 mrs lr, spsr
1041 str lr, [sp, #8] @ save spsr
1042
1043 @
1044 @ Prepare for SVC32 mode. IRQs remain disabled.
1045 @
1046 mrs r0, cpsr
1047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1048 msr spsr_cxsf, r0
1049
1050 @
1051 @ the branch table must immediately follow this code
1052 @
1053 and lr, lr, #0x0f
1054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 mov r0, sp
1057 ARM( ldr lr, [pc, lr, lsl #2] )
1058 movs pc, lr @ branch to handler in SVC mode
1082 .long __irq_usr @ 0 (USR_26 / USR_32)
1083 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1084 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1085 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1086 .long __irq_invalid @ 4
1087 .long __irq_invalid @ 5
1088 .long __irq_invalid @ 6
1089 .long __irq_invalid @ 7
1090 .long __irq_invalid @ 8
1091 .long __irq_invalid @ 9
1092 .long __irq_invalid @ a
1093 .long __irq_invalid @ b
1094 .long __irq_invalid @ c
1095 .long __irq_invalid @ d
1096 .long __irq_invalid @ e
1097 .long __irq_invalid @ f