Verilog —— 四级流水方式的八位全加器

module Four_Adder(out,ina,inb,cin,cout,clk);
 input[7:0] ina,inb;
 input cin,clk;
 output [7:0]out;
 output cout;
 reg [7:0]out;
 reg cout;
 reg[7:0] tempa,tempb,tempci;
 reg[5:0] rega1;
 reg[5:0] rega2;
 
 reg[1:0] firsta1;
 reg[3:0] firstb1;
 reg[5:0] firstc1;
 reg  carya1,caryb1,caryc1;
 reg[3:0]regb1,regb2;
 reg[1:0]regc1,regc2;
 always@(posedge clk)
 begin
   tempa<=ina;
   tempb<=inb;
   tempci<=cin;//数据缓存
 end
 always@(posedge clk)
 begin
 {carya1,firsta1}<=tempa[1:0]+tempb[1:0]+tempci;//第0\1位完成加法 
  rega1[5:0]<=tempa[7:2];
  rega2[5:0]<=tempb[7:2];//数据缓存
 end 
 always@(posedge clk)
 begin
  {caryb1,firstb1}<={rega1[1:0]+rega2[1:0],carya1,firsta1};//第2.3位完成运算 
  regb1[3:0]<=rega1[5:2];
  regb2[3:0]<=rega2[5:2];//数据缓存
 end 
 always@(posedge clk)
 begin
  {caryc1,firstc1}<={regb1[1:0]+regb2[1:0],caryb1,firstb1};//第4.5位完成运算 
  regc1[1:0]<=regb1[3:2];
  regc2[1:0]<=regb2[3:2]; //数据缓存
 end 
 always@(posedge clk)
 begin
  {cout,out}<={regc1[1:0]+regc2[1:0],caryc1,firstc1};//第6.7位完成运算
 end 
 
endmodule