Memory

Reference:

http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02013.htm

www.asic-world.com

RAM:

Syntax

reg [wordsize:0] array_name [0:arraysize]

E.G. reg [7:0] my_memory [0:255];

Here [7:0] is the memory width and [0:255] is the memory depth with the following parameters:

• Width : 8 bits, little endian
• Depth : 256, address 0 corresponds to location 0 in the array.

Storing Data:

my_memory [address] = Data_in;

Reading Data:

Data_out = my_memory [address];

Initializing Memories

$readmemh("file_name",mem_array,start_addr,stop_addr);

Note : start_addr and stop_addr are optional.

module  memory();
reg [7:0] my_memory [0:255];

initial begin
 $readmemh("memory.list", my_memory);
end
endmodule

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Following is the Verilog code for a single port RAM with asynchronous read.

module raminfr (clk, we, a, di, do);  

input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];

always @(posedge clk) begin
if (we)
ram[a] = di;
end
assign do = ram[a];
endmodule

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Following is the Verilog code for a single port RAM with "false" synchronous read.

module raminfr (clk, we, a, di, do);

input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;

always @(posedge clk) begin
if (we)
ram[a] = di;
do = ram[a];
end

endmodule

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The following descriptions, featuring an additional reset of the RAM output, are also only mappable onto Distributed RAM with an additional resetable buffer on the data output as shown in the following figure:

module raminfr (clk, we, rst, a, di, do);


input clk;  
input we;  
input rst; 
input  [4:0] a;  
input  [3:0] di;  
output [3:0] do;  
reg    [3:0] ram [31:0];  
reg    [3:0] do;


  always @(posedge clk) begin  
    if (we)  
      ram[a] = di;  
    if (rst)  
      do = 4'b0;  
    else  
      do = ram[a];  
  end  
endmodule

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Following is the Verilog code for a single-port RAM with synchronous read (read through).

module raminfr (clk, we, a, di, do);


input clk;  
input we;  
input  [4:0] a;  
input  [3:0] di;  
output [3:0] do;  
reg    [3:0] ram [31:0];  
reg    [4:0] read_a;


  always @(posedge clk) begin  
    if (we)  
      ram[a] = di;  
    read_a = a;  
  end  
  assign do = ram[read_a];  
endmodule

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