Quartus与vivado fifo IP核需要额外注意的几个点

使用 Quartus与vivado fifo IP核需要额外注意的几个点

IP different input and output width

Quartus fifo different input and output width

Writing 16-bit Words and Reading 8-bit Words

This figure shows an example of a wide write port (16-bit input) and a narrow read port (8-bit output).

In this example, the read port is operating at twice the frequency of the write port. Writing two 16-bit words to the FIFO buffer increases the wrusedw flag to two and the rusedw flag to four. Four 8-bit read operations empty the FIFO buffer. The read begins with the least-significant 8 bits from the 16-bit word written followed by the mostsignificant 8 bits.

Writing 8-Bit Words and Reading 16-Bit Words

This figure shows an example of a narrow write port (8-bit input) with a wide read port (16-bit output).

In this example, the read port is operating at half the frequency of the write port. Writing four 8-bit words to the FIFO buffer increases the wrusedw flag to four and the rusedw flag to two. Two 16-bit read operations empty the FIFO. The first and second 8-bit word written are equivalent to the LSB and MSB of the 16-bit output words, respectively. The rdempty signal stays asserted until enough words are written on the narrow write port to fill an entire word on the wide read port.

Vivado fifo ip different input and output width

Non-symmetric aspect ratios allow the input and output depths of the FIFO to be different. The following write-to-read aspect ratios are supported: 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1. This feature is enabled by selecting unique write and read widths when customizing the FIFO using the Vivado IP Catalog. By default, the write and read widths are set to the same value (providing a 1:1 aspect ratio); but any ratio between 1:8 to 8:1 is supported, and the output depth of the FIFO is automatically calculated from the input depth and the write and read widths.

For non-symmetric aspect ratios, the full and empty flags are active only when one complete word can be written or read. The FIFO does not allow partial words to be accessed. For example, assuming a full FIFO, if the write width is 8 bits and read width is 2 bits, you would have to complete four valid read operations before full deasserts and a write operation accepted. Write data count shows the number of FIFO words according to the write port ratio, and read data count shows the number of FIFO words according to the read
port ratio.

Writing 8-bit Words and Reading 2-bit Words

This is an example of a FIFO with an aspect ratio of 4:1 (write width of 8, read width of 2). In this example, a single write operation is performed, after which four read operations are executed. The write operation is 11_00_01_11. When a read operation is performed, the data is received left to right (MSB to LSB). As shown, the first read results in data of 11, followed by 00, 01, and then 11.

This is an example which shows din, dout, and the handshaking signals for a FIFO with an aspect ratio of 4:1. After a single write, the FIFO deasserts empty. Because no other writes occur, the FIFO reasserts empty after four reads.

Writing 2-bit Words and Reading 8-bit Words

This is an example of a FIFO with a 1:4 aspect ratio (write width = 2, read width = 8). In this figure, four consecutive write operations are performed before a read operation can be performed. The first write operation is 01, followed by 00, 11, and finally 10. The memory is filling up from the left to the right (MSB to LSB). When a read operation is performed, the received data is 01_00_11_10.

This is an example which shows din, dout and the handshaking signals for a FIFO with a 1:4 aspect ratio. After four words are written into the FIFO, empty is deasserted. Then after a single read operation, empty is asserted again.

从上面的的官方文档说明,两家的fifo IP 核不同位宽读写数据的数据填充方式是相反的.
简单来说:

• 大位宽写入,小位宽读出: altera FPGA先从被写入数据的低位部分开始取数,xilinx FPGA先从被写入数据的高位部分开始取数
• 小位宽写入,大位宽读出:altera FPGA会从被读取数据的低位开始填充,xilinx FPGA则会会从被读取数据的高位开始填充.

复位问题

Quartus FIFO sclr 信号

Quartus FIFO Synchronous Clear and Asynchronous Clear Effect

The FIFO Intel FPGA IP core supports the synchronous clear (sclr) and asynchronous clear (aclr) signals, depending on the FIFO modes.The effects of these signals are varied for different FIFO configurations. The SCFIFO supports both synchronous and asynchronous clear signals while the DCFIFO support asynchronous clear signal and asynchronous clear signal that synchronized with the write and read clocks.

Synchronous Clear and Asynchronous Clear in the SCFIFO

• The read and write pointers reset to zero upon assertion of either the sclr or aclr signal.
• The first data word shown after the reset is not a valid Show-ahead data. It reflects the data where the read pointer is pointing to because the q output is not registered. To obtain a valid show-ahead data, perform a valid write after the reset.

Asynchronous Clear in DCFIFO

• The wrreq signal must be low when the DCFIFO comes out of reset (the instant when the aclr signal is deasserted) at the rising edge of the write clock to avoid a race condition between write and reset. If this condition cannot be guaranteed in your design, the aclr signal needs to be synchronized with the write clock. This can be done by setting the Add circuit to synchronize ‘aclr’ input with ‘wrclk’ option from the FIFO parameter editor, or setting the WRITE_ACLR_SYNCH parameter to ON.
• Even though the aclr signal is synchronized with the write clock, asserting the aclr signal still affects all the status flags asynchronously.
• Even though the aclr signal is synchronized with the read clock, asserting the aclr signal affects all the status flags asynchronously.
• For Stratix and Cyclone series, the DCFIFO only supports registered q output in Normal mode,and unregistered q output in Show-ahead mode. For other devices, you have an option to register or unregister the q output (regardless of the Normal mode or Show-ahead mode) in the FIFO parameter editor or set through the ADD_RAM_OUTPUT_REGISTER parameter.

xilinx fifo Resets

Synchronous Reset

The synchronous reset (srst) synchronously resets all counters, output registers and memories when asserted. Because the reset pin is synchronous to the input clock and there is only one clock domain in the FIFO, no additional synchronization logic is necessary.

• For FIFOs built with First-Word-Fall-Through and ECC configurations, the sbiterr and dbiterr may be high until a valid read is performed after the de-assertion of both wr_rst and rd_rst.

Asynchronous Reset

The asynchronous reset (rst) input asynchronously resets all counters, output registers,and memories when asserted. When reset is implemented, it is synchronized internally to the core with each respective clock domain for setting the internal logic of the FIFO to a known state. This synchronization logic allows for proper timing of the reset logic within the core to avoid glitches and metastable behavior.

Note: If the asynchronous reset is one slowest clock wide and the assertion happens very close tothe rising edge of slowest clock, then the reset detection may not happen properly causingunexpected behavior. To avoid such situations, it is always recommended to have the asynchronous reset asserted for at least 3 or C_SYNCHRONIZER_STAGE (whichever is maximum) slowest clock cycles, though this guide talks about one clock wide reset at some places.
FIFO Asynchronous Reset Timing With Safety Circui

Asynchronous Reset Values for Block, Distributed, and Shift RAM FIFOs

When reset is asserted, the full flags are asserted to prevent writes to the FIFO during reset.

总结：

• INTEL FPGA的FIFO的clr信号 或者xilinx 家的FIFO的 reset信号在同步fifo 或者异步FIFO中的使用都有一定的时序要求。具体使用时序要求回顾上述内容或者阅读相关官方文档
• 使用建议：一般情况下，不管使用同步fifo 还是异步fifo时，复位信号 （INTEL FPGA的FIFO的aclr信号 或者xilinx 家的FIFO的 reset信号）都在相应的（慢）时钟下置位8个时钟单元，之后再过60个相应的（慢）时钟单元后，再对fifo进行使用。当然，这样可以做到一套代码对同步fifo ，异步fifo 都起作用。

分享不易，看完点个赞呗。

参考

FIFO Intel® FPGA IP User Guide：ug_fifo.pdf
Xilinx FIFO Generator v13.2：pg057-fifo-generator