PAE

 

PAE

如何从32位线性地址映射到36位物理地址？？

The 64 GB of RAM are split into 224 distinct page frames, and the physical address field of Page Table entries has been expanded from 20 to 24 bits. Because a PAE Page Table entry must include the 12 flag bits (described in the earlier section "Regular Paging") and the 24 physical address bits, for a grand total of 36, the Page Table entry size has been doubled from 32 bits to 64 bits. As a result, a 4-KB PAE Page Table includes 512 entries instead of 1,024.

页表项中的物理地址字段从20变为24，加上另外的12位标识，供36位，因此页表项大小从32变为64，翻倍。

 

骗局。。。

 

1、4K：

PDPT PD PT Offset

 2    9  9  12

 

2、2M

PDPT PD Offset

2    9    21

 

64-bit paging

Platform name | Page size | Number of address bits used | Number of paging levels | Linear address splitting

x86_64           4 KB               48                     4                        9 + 9 + 9 + 9 + 12

 

Translation Lookaside Buffers (TLB)

 

 

Paging in Linux

Page Global Directory        PGDIR_SHIFT

Page Upper Directory（可选）  PUD_SHIFT

Page Middle Directory（可选） PMD_SHIFT

Page Table                   PAGE_SHIFT

When PAE is disabled, PGDIR_SHIFT yields the value 22 (the same value yielded by PMD_SHIFT and by PUD_SHIFT), PGDIR_SIZE yields 222 or 4 MB, and PGDIR_MASK yields 0xffc00000. 

Conversely, when PAE is enabled, PGDIR_SHIFT yields the value 30 (12 from Offset plus 9 from Table plus 9 from Middle Air), PGDIR_SIZE yields 230 or 1 GB, and PGDIR_MASK yields 0xc0000000.