第五节：C64+ DSP 部分术语翻译

本人根据对DSP的理解翻译部分重要的术语，不能保证术语本身翻译的准确性，但是可以保证对术语解释部分翻译的意思基本正确。

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英文原版来自于TMS320C64X+ DSP Cache User's Guide

1.3节。Cache Terms and Definitions

Table 1-1 Cache Terms and Definitions

Ti 定义了若干与片上结构有关的术语，对这些术语的理解是掌握片上结构的必要条件。

1:allocation :The process of finding a location in the cache to store newly cached data. This process can include
evicting data that is presently in the cache to make room for the new data.

将最新的需要缓存的数据在缓存中找到一个位置进行存储的过程（这个位置通常是指一个缓存行）。

这个过程也包括了将此位置的原有缓存（行）数据驱逐出去，从而给新数据让出空间的情况。

 

2:hit: A cache hit occurs when the data for a requested memory location is present in the cache. The
opposite of a hit is a miss. A cache hit minimizes stalling, since the data can be fetched from the cache
much faster than from the source memory. The determination of hit versus miss is made on each level
of the memory hierarchy separately-a miss in one level may hit in a lower level.

当所需要访问的数据正好在缓存中的对应location时时，我们称之为hit，相
反的一种情形则是缺失（miss），缓存命中会减低阻塞发生的几率，因为数据可
以直接从速度很快的缓存中取得，在一个存储器分级的系统中（例如C64+ DSP,存储器分L1,L2,DDR2,这个就是分级），

缓存是否命中与该缓存所处的级别无关—即某一级别的缓存缺失的情况下，其下一级别的缓存
可能是命中的

3.miss:

A cache miss occurs when the data for a requested memory location is not in the cache. A miss may
stall the requestor while the line frame is allocated and data is fetched from the next lower level of
memory. In some cases, such as a CPU write miss from L1D, it is not strictly necessary to stall the
CPU. Cache misses are often divided into three categories: co