module Fetch_Decode(
input wire clk,
input wire stall_id,
input wire[1:0] stall_branch_t,
input wire[31:0] InstrF,
input wire[31:0] PCPlus4F,
output reg[31:0] InstrD,
output reg Is_First,//判断是第几次译码
output reg[31:0] PCPlus4D
);
reg [31:0] last_InstrD;
reg [31:0] last_PCPlus4D;
always @(posedge clk) begin
if (stall_branch_t==2'b01) begin
InstrD <=32'h0;
last_InstrD <= 32'h0;
PCPlus4D <= 32'h0;
last_PCPlus4D <= 32'h0;
Is_First <= 1'b1;
end else begin
if (stall_id==1'b0) begin
InstrD <=InstrF;
last_InstrD <= InstrF;
PCPlus4D <= PCPlus4F;
last_PCPlus4D <= PCPlus4F;
Is_First <= 1'b1;
end else begin
InstrD <=last_InstrD;
PCPlus4D <= last_PCPlus4D;
Is_First <= 1'b0;
end
end
end
endmodule
cpu之Fetch_Decode
最新推荐文章于 2024-05-13 09:33:30 发布