cpu之stall_ctr

module stall_ctr(
	input wire rst,
	input wire clk,
	input wire stall_id,
	input wire stall_branch,//分支暂停
	output reg[1:0] stall_branch_t,
	output reg stall_id_t
);


/*always @(negedge clk) begin
	if (stall_branch_t!=2'b00) begin
		stall_branch_t<= stall_branch_t -2'h1;
	end
	
end*/

always @(rst,clk,stall_id,stall_branch) begin//*********
	if (rst==1'b1) begin
		stall_id_t <= 1'b0;
		stall_branch_t <= 2'b00;
	end else begin
		stall_id_t <= stall_id;
		if (stall_branch==1'b1&&stall_branch_t == 2'b00) begin
			stall_branch_t <= 2'b11;
		end
		if (stall_branch_t!=2'b00&&clk==1'b0) begin
		
		      stall_branch_t<= stall_branch_t -2'h1;
	  end
	end
end


endmodule