omap_prcm_PM

原文地址：http://lhsblog01.blog.163.com/blog/static/102004519201022110333796/

//*****************prcm*******************************************************

power reset and clock managment.

PM由三个架构模块组成： power, clock, voltage.

clock domain: 使用同一个clk作为时钟输入的所有模块 

voltage domain: 使用同一个 voltage regulator，的所有模块

power domain: 由同一个电源控制基础设施控制的所有模块。

：电源控制基础设施，由momery, logic组成

关系：

power domain 可以跨多个voltage domain

一个power domain 对应可以有多个 clock domain. 当所有的clock domain 关闭后，才关闭这个 power domain

Architectural Blocks for Power Management

    The device supports the power-management techniques through three architectural blocks: the power,

    clock, and voltage domains. A domain is a group of modules or subsections of the device that share a

    common entity (clock, voltage, or power switching).

代码实现以上的概念时，以模块的形式组织

全局变量，宏，结构定义，导出操作接口。

/* clkdm_list contains all registered struct clockdomains */

static LIST_HEAD(clkdm_list);

/* clkdm_mutex protects clkdm_list add and del ops */

static DEFINE_MUTEX(clkdm_mutex);

//********clk*********

32K＿CLK：主要是用于RTC时钟的，

SYS＿CLK： System clock. Serves as primary source clock of the device. Also used as functional and interface clock for PRM.

SYS_32K:

 4.7.2.1.1 32-kHz Always-On Clock

 The sys_32k input pin supplies the 32-kHz always-on clock (32K_FCLK clock). This clock is used for

 low-frequency operation (timers, debouncing, etc.). It also supplies the WKUP power domain for operation

 in the lowest power mode.

SYS＿CLK：

The high-frequency system clock (SYS_CLK) is supplied to the device from an external clock source

through the sys_xtalin input pin or is generated internally by a local system clock crystal oscillator.

OMAP43XX内部能产生时钟：

1：PRM

2：DPLL

3：CM

DPLL3产生4种频率：

L3＿ICLK L3总线频率

L4＿ICLK L4总线频率。

DPLL4产生5种频率，供给外设。

DPLL4 generates clocks for the peripherals, supplying five clock sources:

? 96-MHz always-on source clock for the PRM

? 54-MHz to TV DAC

? Display functional clock

? Camera sensor clock

? Emulation trace clock

DPLL5接受SYS＿CLK并产生1个外设可用的频率。

   ? 120-MHz functional clock to the peripheral domain modules

只需要L3：

IVA2.2 asynchronous bridges

All memory controllers (OCM ROM, OCM RAM, SDRC, SMS, and GP

需要L3及L4

SDMA

HS USB

需要L4

SCM

Mailboxes

ICR

Modem INTC All peripherals (McBSP1, McBSP5, MMC1, MMC2, , I2C1, I2C2, I2C3, McSPI1,McSPI2, McSPI3, McSPI4, UART1, UART2, HDQ, GPTIMER10, and GPTIMER11)

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