armv7系统的exception vector设置

本文摘自arm文档：ARM? Architecture Reference Manual ARMv7-A and ARMv7-R edition

1、Implementation that does not include the Security Extensions

This section applied to all ARMv7-R implementations.

An implementation that does not include the Security Extensions has a single vector table, the base

address of which is selected by SCTLR.V, see SCTLR, System Control Register, VMSA on

page B4-1707 or SCTLR, System Control Register, PMSA on page B6-1932:

V == 0 Exception base address = 0x00000000. This setting is referred to as normal vectors, or as

low vectors.

V == 1 Exception base address = 0xFFFF0000. This setting is referred to as high vectors, or

Hivecs.

Note

ARM deprecates using the Hivecs setting, SCTLR.V == 1, in ARMv7-R. ARM recommends that

Hivecs is used only in ARMv7-A implementations.

2、Implementation that includes the Security Extensions

Any implementation that includes the Security Extensions has the following vector tables:

? One for exceptions taken to Secure Monitor mode. This is the Monitor vector table, and is in

the address space of the Secure PL1&0 translation regime.

? One for exceptions taken to Secure PL1 modes other than Monitor mode. This is the Secure

vector table, and is in the address space of the Secure PL1&0 translation regime.

? One for exceptions taken to Non-secure PL1 modes. This is the Non-secure vector table, and

is in the address space of the Non-secure PL1&0 translation regime.

For the Monitor vector table, MVBAR holds the exception base address.

For the Secure vector table:

? the Secure SCTLR.V bit determines the exception base address:

V == 0 The Secure VBAR holds the exception base address.

V == 1 Exception base address = 0xFFFF0000, the Hivecs setting.

For the Non-secure vector table:

? the Non-secure SCTLR.V bit determines the exception base address:

V == 0 The Non-secure VBAR holds the exception base address.

V == 1 Exception base address = 0xFFFF0000, the Hivecs setting.

3、Implementation that includes the Virtualization Extensions

An implementation that includes the Virtualization Extensions must include the Security

Extensions, and also includes an additional vector table. Therefore, it has the following vector

tables:

? One for exceptions taken to Secure Monitor mode. This is the Monitor vector table, and is in

the address space of the Secure PL1&0 translation regime.

? One for exceptions taken to Secure PL1 modes other than Monitor mode. This is the Secure

vector table, and is in the address space of the Secure PL1&0 translation regime.

? One for exceptions taken to Hyp mode, the Non-secure PL2 mode. This is the Hyp vector

table, and is in the address space of the Non-secure PL2 translation regime.

? One for exceptions taken to Non-secure PL1 modes. This is the Non-secure vector table, and

is in the address space of the Non-secure PL1&0 translation regime.

The exception base addresses of the Monitor vector table, the Secure vector table, and the

Non-secure vector table are determined in the same way as for an implementation that includes the

Security extensions but not the Virtualization extensions.

For the Hyp vector table, HVBAR holds the exception base address